0X2C-Subsystem Id And Subsystem Vendor Id Register; 0X34-Capabilities Pointer Register; 0X3C-Interrupt Line, Interrupt Pin, Min_Gnt, Max_Lat Register - Conexant Fusion 878A Manual

Fusion 878A
PCI Video Decoder
0x2C—Subsystem ID and Subsystem Vendor ID Register
Bits Type Default
[31:16] RW 0x0000
[15:0] RW 0x0000
0x34—Capabilities Pointer Register
Bits Type Default
[7:0] RO 0x44
0x3C—Interrupt Line, Interrupt Pin, Min_Gnt, Max_Lat Register
Bits Type Default
[31:24] RO 0xFF
[23:16] RO 0x04
[15:8] RO 0x01
[7:0] RW
100600B
Name
Subsystem ID Vendor specific.
Subsystem Identifies the vendor of the add-on board or subsystem assigned by PCI
Vendor ID SIG.
Name
Cap_Ptr DWORD-aligned byte address offset in configuration space to the first item
in the list of capabilities.
Name
Max_Lat Requires bus access every 64 µs, at a minimum, in units of 250 ns. Affects
the desired settings for the latency timer value. This register is set to the
max value even though the audio can tolerate up to 287 µs bus access
latency (a 0 setting would indicate no latency requirements).
Min_Gnt Requires a minimum grant burst period of 1 µs to empty data FIFO, in units
of 250 ns. Affects the desired settings for the latency timer value. Set for 32
DWORDs, 33 MHz, with 0 wait states.
Interrupt Pin Fusion 878A interrupt pin is connected to INTA, the only one usable by a
single function device.
Interrupt Line The Interrupt Line register communicates interrupt line routing information
between the POST code and the device driver. The POST code initializes
this register with a value specifying to which input (IRQ) of the system
interrupt controller the Fusion 878A interrupt pin is connected. Device
drivers can use this value to determine interrupt priority and vector
information.
Conexant
6.0 Control Register Definitions–Function 1
6.2 PCI Configuration Registers (Header)
Description
Description
Description
6-5