0X084-Timing Generator Control (Tgctrl) Register - Conexant Fusion 878A Manual

5.0 Control Register Definitions-Function 0
5.3 Local Registers (Memory Mapped)
0x084—Timing Generator Control (TGCTRL) Register
Upon reset, TGCTRL is initialized to 00.
7
[6:5] RW
[4:3] RW
2 RW
1 RW
0 RW 00
NOTE(S):
(1)
The entire decoder will be running off the external clock GPCLK when GPCLK is activated. Therefore, the decoder
functionality is subject to a halt condition if the input port is disconnected. A clock detect circuit will allow the decoder to fall
back on either the PLL or the XTAL, whichever is enabled via PLL_I. If the PLL has been put to sleep, then the decoder will fall
back on the XTAL0 input. The VPRES status condition indicates the status of the clock detect output when in Digital Video
Input mode, which is monitoring GPCLK.
You should set up the PLL to run at the same frequency as the GPCLK input, so that if the digital camera is disconnected,
blue-field timing will run properly.
5-26
Reserved Must be written with a logical zero.
TGCKO GPCLK Output Clock Select
00 = CLKx1
01 = XTAL 0 input
10 = PLL
11 = PLL – inverted
TGCKI Decoder Input Clock Select.
00 = Normal XTAL 0/XTAL 1 mode
01 = PLL
10 = GPCLK
11 = GPCLK–inverted
TGC_AI Timing Generator Read Address Increment. Active high pulse increments the read
address.
GPC_AR Timing Generator Address Reset.
0 = Read/write mode
1 = Enable timing generator/read mode
Conexant
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(1)
Fusion 878A
PCI Video Decoder
100600B