Fifo Data Interface; Table 2-7. Status Bits - Conexant Fusion 878A Manual

Fusion 878A
PCI Video Decoder

2.11.2 FIFO Data Interface

100600B
Loading data into the FIFO can begin only when valid pixels are present during
the even or the odd field. The pixel DWORD Pixel Data (PD) [31:0] is stored in
FI[31:0], and the video control code STATUS[3:0] is stored in FI[35:32]. The
VBI data will be included in the captured sequence if VBI capture capability is
enabled.
Four bits of STATUS are used to encode information about the pixel data and
the state of video timing unit (see
information, along with the data stream, passes through the FIFO. The FIFO
buffer isolates the asynchronous video input and PCI output domains. Control of
the input stream can occur only from the video timing unit of the video decoder
and from the configured registers. The interaction and synchronization of the
DMA controller and the RISC instruction sequence relies solely on the output
side of the FIFO.

Table 2-7. Status Bits

Status[3:0] Code
0110 FM1
1110 FM3
0010 SOL
0001 EOL
1101 EOL
1001 EOL
0101 EOL
0100 VRE
1100 VRO
0000 PXV
Capturing data to the FIFO always begins with a FIFO mode indicator code
followed by pixel data. The FIFO mode indicator is stored in the FIFOs at the
beginning of every capture-enabled field, when the data format is changed
mid-field such as transitioning from packed VBI data to planar mode, and when
video capture of a field is asynchronously enabled. The mode status codes are
always stored in planar format. FIFO1 receives two copies of the status code,
while FIFO2 and FIFO3 each receive one copy.
The SOL code is packed in the FIFO with the first valid pixel data byte, which
is the first pixel DWORD for the scan line. The EOL code is packed in the FIFO
with the last valid pixel data byte, which is the last DWORD location written to
the FIFO for the scan line. The EOL code indicates 1–4 valid bytes. The
VRE/VRO code is stored in the FIFO at the end of a capture-enabled field. The
DMA controller activates the appropriate PCI byte-enable by the time a given
DWORD arrives on the output side of the FIFO.
The DMA controller guarantees that the FIFO does not fill; therefore the
VDFC has no responsibility for FIFO overruns. The DMA Controller will be able
to resynchronize to data streams that are shorter or longer than expected.
Conexant
Table 2-7). Video timing and control
Description
FIFO Mode: packed data to follow
FIFO Mode: planar data to follow
First active pixel/data DWORD of scan line
Last active pixel/data DWORD of scan line, 4 valid bytes
Last active pixel/data DWORD of scan line, 3 valid bytes
Last active pixel/data DWORD of scan line, 2 valid bytes
Last active pixel/data DWORD of scan line, 1 valid byte
VRESET following an even field–falling edge of FIELD
VRESET following an odd field–rising edge of FIELD
Valid pixel/data DWORD
2.0 Functional Description
2.11 Video and Control Data FIFO
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