Sign In
Upload
Manuals
Brands
Cmsemicon Manuals
Microcontrollers
CMS32H6157
Cmsemicon CMS32H6157 Measurement SoC Manuals
Manuals and User Guides for Cmsemicon CMS32H6157 Measurement SoC. We have
1
Cmsemicon CMS32H6157 Measurement SoC manual available for free PDF download: User Manual
Cmsemicon CMS32H6157 User Manual (822 pages)
Ultra-low-power 32-bit measurement SOC based on the ARM Cortex-M0+
Brand:
Cmsemicon
| Category:
Microcontrollers
| Size: 17 MB
Table of Contents
Contents Document Instructions
2
Table of Contents
3
Cpu
19
Overview
19
Cortex-M0+ Core Features
19
Debugging Features
19
SWD Interface Pins
21
ARM Reference Document
22
Port Function
23
Port General Function
23
Port Multiplexing Function
24
Registers for Controlling Port Functions
27
Port Output Control Register (Pmxx)
29
Port Register (Pxx)
30
Port Set Control Register (Psetxx)
31
Port Clear Control Register (Pclrxx)
32
Pull-Up Resistor Selection Register (Puxx)
33
Pull-Down Resistor Selection Register (Pdxx)
34
Port Output Mode Register (Pomxx)
35
Port Mode Control Register (Pmcxx)
36
Port Readback Register (Preadxx)
37
Port Multiplexing Function Configuration Register (Pxxcfg)
38
External Interrupt Port Selection Register (Intpnpcfg)
41
External Reset Port Mask Register (RSTM)
44
Handling of Unused Ports
45
Register Settings When Using the Multiplexing Function
46
Basic Ideas When Using Multiplexing Functions
46
System Structure
65
Overview
65
System Address Division
66
Peripheral Address Assignment
67
Clock Generation Circuit
68
Function of Clock Generation Circuit
68
Structure of Clock Generation Circuit
70
Registers for Controlling Clock Generation Circuit
73
Clock Operation Mode Control Register (CMC)
73
System Clock Control Register (CKC)
75
Clock Operation Status Control Register (CSC)
76
Status Register of the Oscillation Stabilization Time Counter (OSTC)
78
Oscillation Stabilization Time Selection Register (OSTS)
80
Peripheral Enabled Registers 0, 1 (PER0, PER1)
82
Subsystem Clock Supply Mode Control Register (OSMC)
85
High-Speed Internal Oscillator Frequency Selection Register (HOCODIV)
86
High-Speed Internal Oscillator Trim Register (HIOTRM)
87
Subsystem Clock Selection Register (SUBCKSEL)
88
System Clock Oscillation Circuit
89
X1 Oscillation Circuit
89
XT1 Oscillation Circuit
90
High-Speed Internal Oscillator
93
Low-Speed Internal Oscillator
93
Operation of Clock Generation Circuit
94
Clock Control
96
Example of Setting up a High-Speed Internal Oscillator
96
Example of Setting X1 Oscillation Circuit
98
Example of Setting XT1 Oscillation Circuit
99
CPU Clock State Transition Diagram
100
Conditions before CPU Clock Transfer and Post-Transfer Processing
106
Time Required to Switch CPU Clock and Main System Clock
108
Conditions before Clock Oscillation Stops
109
High-Speed Internal Oscillation Correction
110
High-Speed Internal Oscillation Self-Adjustment Function
110
Register Description
111
High-Speed Internal Oscillation Frequency Correction Control Register (HOCOFC)
111
Action Description
113
Action Summary
113
Action Setting Flow
116
Notes on Use
117
SFR Access
117
Actions on Resetting
117
Oscillation Stop Detection Circuit
118
Composition of the Oscillation-Stop Detection Circuit
118
The Registers Used by the Oscillation-Stop Detection Circuit
119
Peripheral Enabled Register 1(PER1)
119
Oscillation Stop Detection Control Register (SCMCTL)
119
Oscillation Stop Detection Mode Register (SCMMD)
120
Oscillation Stop Detection Status Register (SCMST)
120
Operation of Oscillation Stop Detection Circuit
121
Operation Method of Oscillation Stop Detection Circuit
121
Operation of Oscillation Stop Detection Circuit in Deep Sleep Mode
122
Notes on the Oscillation Stop Detection Function
122
General-Purpose Timer Unit Timer8
123
General-Purpose Timer Unit Functions
125
Independent Channel Operation Functions
125
Multi-Channel Linkage Operation Functions
127
LIN-Bus Support Function (Channel 3 Only)
129
Structure of the General-Purpose Timer Unit
130
General-Purpose Timer Unit Register List
132
Timer Count Register Mn (Tcrmn)
133
Timer Data Register Mn (Tdrmn)
135
Registers that Control the General-Purpose Timer Unit
136
Peripheral Enable Register 0(PER0)
137
Timer Clock Selection Register M (Tpsm)
138
Timer Mode Register Mn (Tmrmn)
141
Timer Status Register Mn (Tsrmn)
145
Timer Channel Enable Status Register M (Tem)
146
Timer Channel Start Register M (Tsm)
147
Timer Channel Stop Register M (Tpsm)
148
Timer Input Output Selection Register (TIOS0)
149
Timer Output Enable Register M (Toem)
150
Timer Output Register M (Tom)
151
Timer Output Level Register M (Tolm)
152
Timer Output Mode Register M (Tomm)
153
Input Switching Control Register (ISC)
154
Noise Filter Enable Register (NFEN1)
155
Registers for Controlling Timer Input/Output Pin Port Functions
156
Basic Rules of the General-Purpose Timer Unit
157
Basic Rules of Multi-Channel Linkage Operation Function
157
Timer Channel Start Register M (Tsm)
160
Operation of Counters
161
Counting Clock (F )
161
Start Timing of Counter
163
Operation of Counters
164
Control of Channel Outputs (Tomn Pins)
169
Block Diagram of the Tomn Pin Output Circuit
169
Settings of the Tomn Pin Output
170
Cautions for Channel Output Operation
171
One-Time Operation of Tomn Bit
176
Timer Interrupt and Tomn Pin Output When Counting Starts
177
Control of Timer Input (Timn)
178
Block Diagram of the Timn Pin Input Circuit
178
Noise Filter
178
Cautions for Channel Input Operation
179
Independent Channel Operation Function for General Purpose Timer Units
180
Operation as Interval Timer/Square Wave Output
180
Operation as External Event Counter
184
Operation as Frequency Divider
187
Operation as Input Pulse Interval Measurement
190
Operation as Input Signal High and Low Level Width Measurement
194
Operation as Delay Counter
198
Multi-Channel Linkage Operation Function for General Purpose Timer Units
201
Operation as Single Trigger Pulse Output Function
201
Operation as PWM Function
208
Operation as Multiple PWM Output Function
215
Cautions When Using the General-Purpose Timer Unit
224
Cautions When Using Timer Output
224
Timera
225
Timera Function
225
Structure of Timer a
226
Registers for Controlling Timer a
227
Peripheral Enable Register 0(PER0)
228
Subsystem Clock Supply Mode Control Register (OSMC)
229
Timer a Count Register 0 (TA0)
230
Timer a Control Register 0 (TACR0)
231
Timer AI/O Control Register 0 (TAIOC0)
232
Timer a Control Register 0 (TAMR0)
234
Timer a Event Pin Selection Register 0 (TAISR0)
235
Timer a Operation
236
Rewriting the Reload Register and Counter
236
Timer Mode
237
Pulse Output Mode
238
Event Counter Mode
239
Pulse Width Measurement Mode
241
Pulse Period Measurement Mode
242
Collaboration with EVENTC
243
Output Settings for each Mode
244
Cautions When Using Timer a
245
Start and Stop Control of Counting
245
Flag Access (TEDGF Bit and TUNDF Bit of TACR0 Register)
245
Access to Counting Registers
246
Change in Mode
246
Setting Procedure for TAO Pin and TAIO Pin
246
When Timer a Is Not Used
247
Stop of Timer a Operation Clock
247
Setting Steps for Deep Sleep Mode (Event Counter Mode)
247
Function Limitations in Deep Sleep Mode (Event Counter Mode Only)
248
Forced Count Stop Via the TSTOP Bit
248
Digital Filters
248
Selecting FIL as the Count Source
249
Real Time Clock
250
Functions of Real-Time Clock
250
Structure of Real-Time Clock
250
Registers for Controlling Real-Time Clock
252
Peripheral Enable Register 0 (PER0)
253
Real-Time Clock Selection Register (RTCCL)
254
Real-Time Clock Control Register 0 (RTCC0)
255
Real-Time Clock Control Register 1 (RTCC1)
256
Watch Error Correction Register (SUBCUD)
258
Second Count Register (SEC)
259
Minute Count Register (MIN)
260
Hour Count Register (HOUR)
261
Day Count Register (DAY)
263
Week Count Register (WEEK)
264
Month Count Register (MONTH)
265
Year Count Register (YEAR)
266
Alarm Minute Register (ALARMWM)
267
Alarm Hour Register (ALARMWH)
268
Alarm Week Register (ALARMWW)
269
Starting Operation of Real-Time Clock
270
Shifting to Sleep Mode after Starting Operation
271
Reading/Writing Real-Time Clock
272
Setting Alarm of Real-Time Clock
274
Hz Output of Real-Time Clock
275
Example of Watch Error Correction of Real-Time Clock
276
15-Bit Interval Timer
278
Functions of 15-Bit Interval Timer
278
Structure of 15-Bit Interval Timer
278
Registers Controlling 15-Bit Interval Timer
279
Peripheral Enable Register 0 (PER0)
279
Real-Time Clock Selection Register (RTCCL)
280
15-Bit Interval Timer Control Register (ITMC)
281
15-Bit Interval Timer Operation
282
15-Bit Interval Timer Operation Timing
282
Start of Count Operation and Re-Enter to Sleep Mode after Returned from Sleep Mode
283
Clock Output/Buzzer Output Controller
284
Functions of Clock Output/Buzzer Output Controller
284
Registers for Controlling Clock Output/Buzzer Output Controller
286
Clock Output Select Registers N (Cksn)
286
Operations of Clock Output/Buzzer Output Controller
288
Cautions of Clock Output/Buzzer Output Controller
288
Watch Dog Timer
289
Functions of Watchdog Timer
289
Structure of Watch Dog Timer
289
Registers for Controlling Watchdog Timer
291
Watchdog Timer Enable Register (WDTE)
291
LOCKUP Control Register (Lockctl)And Its Protection Register(PRCR)
292
WDTCFG Configuration Registers (WDTCFG0/1/2/3)
293
Operation of Watchdog Timer
294
Operational Control of Watchdog Timer
294
Setting Overflow Time of Watchdog Timer
296
Setting Window Open Period of Watchdog Timer
297
Setting Watchdog Timer Interval Interrupt
298
Operation of the Watchdog Timer During LOCKUP
298
Operation of the Watchdog Timer Without WDTCFG Configured
298
Ad Converter
299
Function of A/D Converter
299
Registers for Controlling A/D Converter
301
Peripheral Enable Register (PER1)
302
A/D Converter Mode Register 0 (ADM0)
303
A/D Converter Mode Register 1 (ADM1)
304
A/D Converter Mode Register 2 (ADM2)
305
A/D Converter Trigger Mode Register (ADTRG)
306
Analog Input Channel Specification Register (ADS)
307
12-Bit A/D Conversion Result Register (ADCR)
310
8-Bit A/D Conversion Result Register (ADCRH)
311
Conversion Result Comparison Upper Limit Setting Register (ADUL)
311
Conversion Result Comparison Lower Limit Setting Register (ADLL)
312
A/D Converter Sampling Time Control Register (ADNSMP)
313
A/D Converter Sampling Time Extension Control Register (ADSMPWAIT)
315
A/D Test Register (ADTES)
316
A/D Converters Charge-Discharge Control Register (ADNDIS)
317
Input Voltage and Conversion Result
318
Operation Mode of A/D Converter
319
Software Trigger Mode (Select Mode, Sequential Conversion Mode)
319
Software Trigger Mode (Select Mode, Single Conversion Mode)
320
Software Trigger Mode (Scan Mode, Sequential Conversion Mode)
321
Software Trigger Mode (Scan Mode, Single Conversion Mode)
322
Hardware Trigger No-Wait Mode (Select Mode, Sequential Conversion Mode)
323
Hardware Trigger No-Wait Mode (Select Mode, Single Conversion Mode)
324
Hardware Trigger No-Wait Mode (Scan Mode, Sequential Conversion Mode)
325
Hardware Trigger No-Wait Mode (Scan Mode, Single Conversion Mode)
326
Hardware Trigger Wait Mode (Select Mode, Sequential Conversion Mode)
327
Hardware Trigger Wait Mode (Select Mode, Single Conversion Mode)
328
Hardware Trigger Wait Mode (Scan Mode, Sequential Conversion Mode)
329
Hardware Trigger Wait Mode (Scan Mode, Single Conversion Mode)
330
A/D Converter Setup Flowchart
331
Setting up Software Trigger Mode
331
Setting up Hardware Trigger No-Wait Mode
332
Setting up Hardware Trigger Wait Mode
333
Setup When Temperature Sensor Output Voltage/Internal Reference Voltage Is Selected
334
Setting up Test Mode
335
Sigma-Delta Adc
336
Overview
336
Description of Basic Functions
336
Description of ADC Working Principle
337
Ldo
337
Analog Inputs
337
Temperature Sensor
337
Low Noise Programmable Gain Amplifier
337
ADC Clock, Output Data Rate
338
Reset and Sleep Mode
339
Setup Time
339
SPI Serial Interface
340
Digital Output Codes
340
Data Ready/Data Input and Output (DRDYB/DOUT)
340
Serial Input Clock (SCLK)
340
Serial Data Transmission
341
Function Configuration
342
Description of SPI Opcode Command
343
Cautions for SPI Communication
343
Related Registers
344
Sigma-Delta ADC Control Register 1
344
Sigma-Delta ADC Control Register 2
345
Sigma-Delta ADC Control Register 3
346
Sigma-Delta ADC Control Register 4
347
D/A Converter
348
Function of D/A Converter
348
Structure of D/A Converter
349
Registers for Controlling D/A Converter
350
Peripheral Enable Register 1 (PER1)
350
D/A Converter Mode Register (DAM)
351
D/A Conversion Value Setting Register I (Dacsi) (I=0)
351
Event Output Destination Select Register N (Elselrn), N= 00~15
351
Operation of D/A Converter
352
Operation in Normal Mode
352
Operation in Real-Time Output Mode
353
D/A Conversion Output Timing
354
Cautions for D/A Converter
355
Comparator
356
Function of Comparator
356
Structure of Comparator
357
Registers for Controlling Comparator
359
Peripheral Enable Register 1 (PER1)
360
Comparator Mode Setting Register (COMPMDR)
361
Comparator Filter Control Register (COMPFIR)
362
Comparator Output Control Register (COMPOCR)
364
Comparator Negative Reference Selection Register (Cnrefs)
366
Comparator Positive Input Selection Register (Cmpseln)
367
Comparator Hysteresis Control Register (Cmpnhy)
368
Operation
369
Digital Filter of Comparator N (N=0, 1)
371
Comparator N Interrupt (N=0, 1)
371
Event Signal Output to the Coordination Controller (EVENTC)
372
Output of Comparator N (N=0, 1)
373
Stopping or Supplying Comparator Clock
374
Operational Amplifier (Opa)
375
Function of Operational Amplifier
375
Register of Operational Amplifier
376
Peripheral Enable Register 1 (PER1)
376
Operational Amplifier Control Register (OPACTL)
377
Operational Amplifier Digital-To-Analog Control Register (OPADAC)
378
General-Purpose Serial Communication Unit
379
Function of General-Purpose Serial Communication Unit
380
3-Wire Serial I/O (SSPI00, SSPI01, SSPI10, SSPI11, SSPI20, SSPI21)
380
Uart (Uart0~Uart2)
381
Simplified I C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21)
382
Structure of General-Purpose Serial Communication Unit
383
Shift Register
385
Serial Data Register Mn (Sdrmn)
385
Registers for Controlling General-Purpose Serial Communication Unit
387
Peripheral Enable Register 0 (PER0)
389
Serial Clock Selection Register M (Spsm)
390
Serial Mode Register Mn (Smrmn)
391
Serial Communication Run Setting Register Mn (Scrmn)
393
Serial Data Register Mn (Sdrmn)
396
Serial Flag Clear Trigger Register Mn(Sirmn)
397
Serial Status Register Mn (Ssrmn)
398
Serial Channel Start Register M(Ssm)
400
Serial Channel Stop Register M(Stm)
401
Serial Channel Enable Status Register M (Sem)
402
Serial Output Enable Register M (Soem)
403
Serial Output Register M (Som)
404
Serial Output Level Register M (Solm)
405
Serial Standby Control Register M (Sscm)
406
Slave Select Function Enable Register M (Ssem)
407
Input Switching Control Register (ISC)
408
Noise Filter Enable Register 0 (NFEN0)
409
Operation Stop Mode
410
Stopping the Operation by Units
410
Stopping the Operation by Channels
411
3-Wire Serial I/O(SSPI00, SSPI01, SSPI10, SSPI11, SSPI20, SSPI21) Communication
412
Master Transmission
413
Master Reception
421
Master Transmission and Reception
429
Slave Transmission
437
Slave Reception
445
Slave Transmission and Reception
451
Calculation of Transmission Clock Frequency
460
Procedure for Handling Errors During 3-Wire Serial I/O Communication
462
Sspi11, Sspi20, Sspi21)
462
Operation of Clock-Synchronous Serial Communication with Slave Selection Input Function
463
Slave Transmission
466
Slave Reception
476
Slave Transmission and Reception
483
Calculation of Transmission Clock Frequency
493
Procedure for Handling Errors During Clock-Synchronous Serial Communication with the Slave Selection Input Function
494
Operation of UART (UART0~UART2) Communication
495
UART Transmission
496
UART Reception
504
Low-Power UART Mode Function
511
Calculation of Baud Rate
517
Handling Steps When an Error Occurs During UART (UART0~UART2) Communication
521
Operation of LIN Communication
522
LIN Transmission
522
LIN Reception
525
Operation of Simple I C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21) Communication
530
Address Segment Sending
531
Data Transmission
536
Data Reception
539
Generation of Stop Condition
543
Calculation of Transfer Rate
544
Processing Steps When an Error Occurs in a Simple I
546
C (Iic00, Iic01, Iic10, Iic11, Iic20, Iic21)
546
Communication Process
546
Serial Interface Spi
547
Function of SPI
547
Structure of SPI
547
Registers for Controlling SPI
548
Peripheral Enable Register 1 (PER1)
548
SPI Operating Mode Register (SPIM)
549
SPI Clock Selection Register (SPIC)
550
SPI Status Register (SPIS)
551
Transmit Buffer Register (SOTB)
552
Receive Buffer Register (SIO)
552
Operation of SPI
553
Master Tramission and Reception
554
Master Reception
557
Slave Transmission and Reception
560
Slave Reception
563
Serial Interface Iica
566
Function of IICA
566
Run Stop Mode
566
C-Bus Mode (Supports Multi-Master)
566
Wake-Up Mode
566
Structure of IICA
569
IICA Shift Register N (Iican)
570
Slave Address Register N(Svan)
570
SO Latch
570
Wake-Up Control Circuitry
571
Serial Clock Counter
571
Interrupt Request Signal Generation Circuit
571
Serial Clock Control Circuitry
571
Serial Clock Wait Control Circuit
571
Ack Generation Circuit, Stop Condition Detection Circuit, Start Condition Detection Circuit, Ack Detection Circuit
571
Data Hold Time Correction Circuit
571
Start Conditional Generation Circuitry
571
Stop Condition Generation Circuitry
572
Bus Status Detection Circuitry
572
Registers for Controlling IICA
573
Peripheral Enable Register 0 (PER0)
573
IICA Control Register N0 (Iicctln0)
574
IICA Status Register N(Iicsn)
578
IICA Flag Register N(Iicfn)
581
IICA Control Register N1(Iicctln1)
583
IICA Low-Level Width Setting Register N(Iicwln)
585
IICA High Level Width Setting Register N(Iicwhn)
585
Registers for Controlling the IICA Pin Port Function
586
Function of I C-Bus Mode
587
Pin Structure
587
Setting the Transmit Clock Via Iicwln Register and Iicwhn Register
588
Definition and Control Method of I C-Bus
590
Start Condition
591
Address
592
Designation of Transmission Direction
592
Ack
593
Stop Condition
594
Await
595
Method of Release from Wait State
597
Generation Timing and Waiting Control of Interrupt Requests (Intiican)
598
Detection Method for Address Matching
599
Error Detection
599
Extension Code
600
Arbitration
601
Wake-Up Function
603
Communication Appointment
606
Other Cautions
610
Communication Operation
611
Timing of I C Interrupt Request (Intiican) Generation
621
Timing Diagram
641
Irda
658
Function of Irda
658
Registers for Controlling Irda
659
Peripheral Enable Register 0 (PER0)
659
Irda Control Register (IRCR)
660
Operation of Irda
661
Procedure for Irda Communication
661
Transmission
662
Reception
662
Selection of High Level Pulse Width
663
Cautions When Using Irda
664
Lcd Controller/Driver
665
Function of LCD Controller / Driver
665
Structure of LCD Controller / Driver
666
Registers for Controlling LCD Controller/Driver
668
LCD Mode Register 0(LCDM0)
669
LCD Mode Register 1(LCDM1)
671
Subsystem Clock Supply Mode Control Register (OSMC)
673
LCD Clock Control Register 0 (LCDC0)
674
LCD Boost Level Control Register (VLCD)
675
LCD Input Switching Control Register (ISCLCD)
677
20.3.7 LCD Port Function Register
678
LCD Display Data Register
679
LCD Display Register Selection
681
20.5.1 Data Display in Graphic Area a and Graphic Area B
682
Blinking Display (Alternate Display of Data in Graph Area a and Graph Area B)
682
LCD Drive Voltage Provided by
683
L1 , V L2 , V L3 , V L4
683
20.6.1 Internal Resistor Splitting Method
683
20.6.2 External Resistance Splitting Method
684
20.6.3 Internal Boost Method
685
20.6.4 Capacitance Splitting Method
686
Enhanced Dma
687
21.1 Function of DMA
687
Structure of DMA
689
Registers for Controlling DMA
690
DMA Control Data Areas and DMA Vector Table Areas Allocation
691
Control Data Allocation
692
Vector Table
694
Peripheral Enable Register 1 (PER1)
696
DMA Control Register J(Dmacrj)(J=0~23)
697
DMA Block Size Register J (Dmblsj)(J=0~23)
699
DMA Transmit Count Register J(Dmactj)(J=0~23)
700
DMA Transfer Count Reload Register J (Dmrldj)(J=0~23)
701
DMA Source Address Register J(Dmsarj)(J=0~23)
702
DMA Destination Address Register J(Dmdarj)(J=0~23)
703
DMA Start Enable Register I (Dmaeni)(I=0~2)
704
DMA Base Address Register (DMABAR)
706
Dmaeni Set Register I(Dmseti)(I=0~2)
707
Dmaeni Reset Register I(Dmclri)(I=0~2)
707
Operation of DMA
708
Startup Source
708
Normal Mode
709
Repeat Pattern
712
Chain Transmission
715
Cautions When Using DMA
717
DMA Control Data and Vector Table Settings
717
Allocation of DMA Control Data Area and DMA Vector Table Area
717
Number of Execution Clocks for DMA
718
Response Time of DMA
719
Startup Source of DMA
719
Operation in Standby Mode
720
Linkage Controller (Eventc)
721
Function of EVENTC
721
Structure of EVENTC
721
Control Register
722
Output Target Selection Register N(Elselrn)(N=00~15)
723
Operation of EVENTC
726
Interrupt Function
728
Types of Interrupt Function
728
Interrupt Sources and Structures
728
Registers for Controlling Interrupt Function
732
Interrupt Request Flag Register (IF00~IF31)
732
Interrupt Mask Flag Register (MK00~MK31)
733
External Interrupt Rising Edge Enable Register (EGP0), External Interrupt Falling Edge Enable Register (EGN0)
735
Operation of Interrupt Handling
736
Acceptance of Maskable Interrupt Requests
736
Acceptance of Non-Maskable Interrupt Requests
736
Key Interrupt Function
737
Function of Key Interrupt
737
Structure of Key Interrupt
737
Register Controlling Key Interrupts
739
Key Return Mode Register (KRM)
739
Standby Function
740
Sleep Mode
741
Setting of Sleep Mode
741
Release of Sleep Mode
745
Deep Sleep Mode
746
Setting of Deep Sleep Mode
746
Release of Deep Sleep Mode
749
Reset Function
750
Reset Timing
752
Register for Confirming the Reset Source
755
Reset Control Flag Register (RESF)
755
Power-On Reset Circuit
757
Function of Power-On Reset Circuit
757
Structure of Power-On Reset Circuit
758
Operation of Power-On Reset Circuit
759
Voltage Detection Circuit
763
Function of Voltage Detection Circuit
763
Structure of Voltage Detection Circuit
764
Registers for Controlling Voltage Detection Circuit
765
Voltage Detection Register (LVIM)
765
Voltage Detection Level Register (LVIS)
766
Operation of Voltage Detection Circuit
769
Settings When Used in Reset Mode
769
Settings When Used in Interrupt Mode
770
Settings for Interrupt & Reset Mode
772
Cautions for Voltage Detection Circuits
779
Security Feature
781
Overview
781
Registers Used for Security Functions
782
Operation of Security Features
783
Flash CRC Operational Function (High-Speed CRC)
783
Flash CRC Control Register (CRC0CTL)
783
Flash CRC Operation Result Register
784
CRC Operation Function (General-Purpose CRC)
786
CRC Input Register (CRCIN)
787
CRC Data Register (CRCD)
787
RAM Parity Error Detection Function
789
RAM Parity Error Control Register (RPECTL)
789
SFR Protection Function
791
SFR Protect Control Register(SFRGD)
791
Frequency Detection Function
792
Timer Input Selection Register0(TIS0)
792
A/D Test Function
793
A/D Test Register (ADTES)
795
Analog Input Channel Specification Register (ADS)
795
Product Unique Identification Register
796
Temperature Sensor and Internal Reference Voltage
797
Temperature Sensor
797
Register for Temperature Sensor
798
Temperature Sensor Calibration Data Register TSN25
798
Temperature Sensor Calibration Data Register TSN85
798
Instructions for Using the Temperature Sensor
799
How Temperature Sensors Are Used
799
How to Use Temperature Sensor
800
Internal Reference Voltage
801
VDD Calibration Data Register VDDCDR
801
Instructions for Using the Internal Reference Voltage
801
Option Bytes
802
Function of Option Bytes
802
User Option Bytes (000C0H~000C2H)
802
Flash Data Protection Option Bytes (000C3H, 500004H)
803
Format of the User Option Bytes
804
Format of Flash Data Protection Option Bytes
810
Flash Control
811
Description of FLASH Control
811
Structure of FLASH Memory
811
Registers for Controlling FLASH
812
Flash Write Protection Register (FLPROT)
812
FLASH Operation Control Register (FLOPMD1,FLOPMD2)
813
Flash Erase Control Register (FLERMD)
814
Flash Status Register (FLSTS)
815
Flash Full-Chip Erase Time Control Register (FLCERCNT)
815
Flash Sector Erase Time Control Register (FLSERCNT)
816
Flash Write Time Control Register (FLPROCNT)
817
Flash Erase Protection Control Register (FLSECPR)
818
How to Operate FLASH
819
Sector Erase
819
Chip Erase
820
Word Program
820
Flash Read
821
Cautions for FLASH Operation
821
Revision History
822
Advertisement
Advertisement
Related Products
Cmsemicon CMS32L051
Cmsemicon CMS32M65 Series
Cmsemicon CMS80F731 Series
Cmsemicon CMS80F751 Series
Cmsemicon CMS8S589 Series
Cmsemicon CMS8S369 Series
Cmsemicon CMS80F261 Series
Cmsemicon CMS80F251 Series
Cmsemicon CMS8S3660
Cmsemicon CMS8S6980
Cmsemicon Categories
Microcontrollers
More Cmsemicon Manuals
Login
Sign In
OR
Sign in with Facebook
Sign in with Google
Upload manual
Upload from disk
Upload from URL