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Artesyn Embedded Technology ATCA-7490 Installation And Use Manual

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ATCA-7490
Installation and Use
P/N: 6806800U11F
December 2018

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Summary of Contents for Artesyn Embedded Technology ATCA-7490

  • Page 1 ATCA-7490 Installation and Use P/N: 6806800U11F December 2018...
  • Page 2 ©Copyright 2018 Artesyn Embedded Technologies, Inc. All rights reserved. Trademarks Artesyn Embedded Technologies, Artesyn and the Artesyn Embedded Technologies logo are trademarks and service marks of Artesyn Embedded Technologies, Inc. All other names and logos referred to are trade names, trademarks, or registered trademarks of their respective owners.

  • Page 3: Table Of Contents

    Serial Interface Connector ......... . . 70 ATCA-7490 Installation and Use (6806800U11F)
  • Page 4 4.19 Real Time Clock ..............103 ATCA-7490 Installation and Use (6806800U11F)
  • Page 5 5.1.14.2 Reset Mask Register ..........150 ATCA-7490 Installation and Use (6806800U11F)
  • Page 6 5.1.28 CPU Error Status Register ........... . 175 ATCA-7490 Installation and Use (6806800U11F)
  • Page 7 6.11 Watchdog Support ..............238 ATCA-7490 Installation and Use (6806800U11F)
  • Page 8 Pigeon Point Specific Commands ........... . 288 ATCA-7490 Installation and Use (6806800U11F)
  • Page 9 Updating ipmitool ..........319 ATCA-7490 Installation and Use (6806800U11F)
  • Page 10 Replacing the Battery ............. . 357 ATCA-7490 Installation and Use (6806800U11F)
  • Page 11 ATCA-7490 Non-Volatile Memory Statement ........
  • Page 12 Contents Contents Contents ATCA-7490 Installation and Use (6806800U11F)
  • Page 13 Power Requirements ............50 Table 2-3 Power Consumption of ATCA-7490 with and without RTM ......51 Table 2-4 Switch SW1 settings .
  • Page 14 Payload Power Failure States ........... .143 ATCA-7490 Installation and Use (6806800U11F)
  • Page 15 RTM SPI Read Register ............171 ATCA-7490 Installation and Use (6806800U11F)
  • Page 16 Advanced >> Memory Configuration ..........219 ATCA-7490 Installation and Use (6806800U11F)
  • Page 17 Feature Configuration Command ..........285 ATCA-7490 Installation and Use (6806800U11F)
  • Page 18 ATCA-7490 Specific Sensors ........
  • Page 19 ATCA-7490 Nonvolatile Memory ........
  • Page 20 List of Tables ATCA-7490 Installation and Use (6806800U11F)
  • Page 21 ATCA-7490 Block Diagram ........
  • Page 22 IPMC block diagram of ATCA-7490 ........

  • Page 23: About This Manual

    251, provides information on how to establish a serial-over LAN  session on your blade. Supported IPMI Commands on page 259, lists all supported IPMI commands.  IPMI Feature Set on page 309, provides information about controlling via IPMI.  ATCA-7490 Installation and Use (6806800U11F)
  • Page 24 About this Manual Replacing the Battery on page 357, provides the battery exchange procedures.  ATCA-7490 Declassification Procedure on page 361, identifies the type, purpose, and  procedures to declassify (erase or reinitialize) the non-volatile memory devices to be found on the ATCA-7490 processor card.
  • Page 25 Processor Power Control Unit Power Entry Module PICMG PCI Industrial Computer Manufacturers Group Power Input Module PCI Mezzanine Card POST Power-On Self-Test PROM Programmable Read-Only Memory Intel QuickPath Interconnect Reliability and Serviceability Real Time Clock Rear Transition Module ATCA-7490 Installation and Use (6806800U11F)
  • Page 26 Used to characterize user input and to separate it Courier + Bold from system output Reference Used for references and for table and figure descriptions File > Exit Notation for selecting a submenu <text> Notation for variables and keys ATCA-7490 Installation and Use (6806800U11F)
  • Page 27 Indicates a hazardous situation which, if not avoided, may result in minor or moderate injury Indicates a property damage message No danger encountered. Pay attention to important information ATCA-7490 Installation and Use (6806800U11F)

  • Page 28: Table

    243 and default value of SW2.4 in Switch SW2 Settings on page Added a new section SATA RAID Configuration on page 191. Updated Chapter 6, BIOS, on page 183. 6806800U11A June 2016 Initial version ATCA-7490 Installation and Use (6806800U11F)

  • Page 29: Safety Notes

    Class A digital device in this system, pursuant to part 15 of the FCC Rules, EN 55022 Class A respectively. These limits are designed to provide reasonable protection against harmful interference when the system is operated in a commercial environment. ATCA-7490 Installation and Use (6806800U11F)
  • Page 30 Damage of Blade and Additional Devices and Modules Incorrect installation of additional devices or modules may damage the blade or the additional devices or modules. Before installing or removing an additional device or module, read the respective documentation ATCA-7490 Installation and Use (6806800U11F)
  • Page 31 A and input line B so that line A remains powered even if it is disconnected from the power supply circuit (and vice versa). To avoid damage or injuries, always check that there is no more voltage on the line that has been disconnected before continuing your work. ATCA-7490 Installation and Use (6806800U11F)
  • Page 32 Therefore, always use the same type of Lithium battery as is installed and make sure the battery is installed as described in this manual. Environment Always dispose of used blades, system components and RTMs according to your country’s legislation and manufacturer’s instructions. ATCA-7490 Installation and Use (6806800U11F)

  • Page 33: Sicherheitshinweise

    Installieren Sie keine Ersatzteile oder führen Sie keine unerlaubten Veränderungen am Produkt durch, sonst verfällt die Garantie. Wenden Sie sich für Wartung oder Reparatur bitte an die für Sie zuständige Geschäftsstelle von Artesyn. So stellen Sie sicher, dass alle sicherheitsrelevanten Aspekte beachtet werden. ATCA-7490 Installation and Use (6806800U11F)
  • Page 34 Bereich mit eingeschränktem Zugang - Installieren Sie das Board in ein System nur in Bereichen mit eingeschränktem Zugang. Datenverlust Wenn Sie das Blade aus dem Shelf herausziehen, und die blaue LED blinkt noch, gehen Daten verloren. Warten Sie bis die blaue LED durchgehend leuchtet, bevor Sie das Blade herausziehen. ATCA-7490 Installation and Use (6806800U11F)
  • Page 35 Bevor Sie das Blade betreiben, müssen Sie sicher stellen, dass das Shelf über eine Zwangskühlung verfügt. Wenn Sie das Blade in Gebieten mit starker elektromagnetischer Strahlung betreiben, stellen Sie sicher, dass das Blade mit dem System verschraubt ist und das System durch ein Gehäuse abgeschirmt wird. ATCA-7490 Installation and Use (6806800U11F)
  • Page 36 Batterie Beschädigung des Blades Ein unsachgemäßer Einbau der Batterie kann gefährliche Explosionen und Beschädigungen des Blades zur Folge haben. Verwenden Sie deshalb nur den Batterietyp, der auch bereits eingesetzt wurde und befolgen Sie die Installationsanleitung. ATCA-7490 Installation and Use (6806800U11F)
  • Page 37 Sicherheitshinweise Umweltschutz Entsorgen Sie alte Batterien und/oder Blades/Systemkomponenten/RTMs stets gemäß der in Ihrem Land gültigen Gesetzgebung und den Empfehlungen des Herstellers. ATCA-7490 Installation and Use (6806800U11F)
  • Page 38 Sicherheitshinweise ATCA-7490 Installation and Use (6806800U11F)

  • Page 39: Introduction

    The ATCA-7490 is a high-performance ATCA PICMG 3.0 R3 compliant single board computer designed for demanding storage and processing applications. The main features of the ATCA-7490 board are as follows: Designed for NEBS Level 3  Dual socket Intel Xeon E5-2600 V4 (Broadwell-EP socket LGA2011-3) ...

  • Page 40: Standard Compliances

    Product is designed to support NEBS level three. The compliance tests must be done with the customer target system. PICMG 3.0 and 3.1 Defines mechanics, blade dimensions, power distribution, power and data connectors, and system management. ATCA-7490 Installation and Use (6806800U11F)

  • Page 41: Mechanical Data

    280 mm +0/-0.3 mm Thickness 2.4 mm + 0.2mm Mounting height top side 21.33 mm (component side 1) Mounting height bottom side 1.61 mm (component side 2) Weight ATCA-7490-0GB: 3.6kg 1. Weight without memories and storage. ATCA-7490 Installation and Use (6806800U11F)

  • Page 42: Product Identification

    Product Identification The following figure shows the location of the QR code and Serial Number of the product. Figure 1-1 Location of Serial Number and QR Code Artesyn internal part number (PCA) QR Code Serial Number ATCA-7490 Installation and Use (6806800U11F)

  • Page 43: Ordering Information

    128GB Slim SATA (MO-297) MLC Module for ATCA-737X, ATCA- 747X, ATCA-748X and ATCA-749X product series, 3Gb SATA I/F. ATCA-7XMMOD-SATA5 256GB Slim SATA (MO-297) MLC Module for ATCA-748X and ATCA- 749X product series, 6Gb SATA I/F. ATCA-7490 Installation and Use (6806800U11F)
  • Page 44 Introduction ATCA-7490 Installation and Use (6806800U11F)

  • Page 45: Hardware Preparation And Installation

    1. Verify that you have received all items of your shipment: One ATCA-7490 blade  One printed copy of Quick Start Guide  One printed copy of Safety Notes Summary  Any optional items ordered  ATCA-7490 Installation and Use (6806800U11F)

  • Page 46: Environmental And Power Requirements

    Environmental Requirements The environmental conditions must be tested and proven in the shelf configuration used. The conditions refer to the surrounding of the blade within the user environment. The ATCA-7490- 0GB-HEL and ATCA-7490-0GB-HEL products support the specified temperature conditions in a shelf with the airflow characteristics meeting at least the CP-TA Class B.4 cooling profile.

  • Page 47: Table 2-1 Environmental Requirements

    5% to 95% non-condensing according to Humidity condensing Telcordia GR-63-CORE (NEBS) and EN 300 019-1-1, Classes 1.2 and 2.3 Exceptional Operation: 5%rH to 90%rh non-condensing According to Telcordia GR-63-CORE (NEBS) and EN 300 019-1-3, Classes 3.1 and 3.1E ATCA-7490 Installation and Use (6806800U11F)

  • Page 48: Table

    (according to Telcordia GR-63-CORE) Shock Half-sine, 11 ms, 30 m/s Blade level packaging Half-sine, 6 ms at 180 m/s Free Fall 1.2 m/ packaged (according to ETSI 300 019-2-2) 100 mm unpackaged (according to Telcordia GR-63-core) ATCA-7490 Installation and Use (6806800U11F)

  • Page 49: Figure 2-1 Location Of Critical Temperature Spots (Blade - Top Side)

    Figure 2-1 Location of Critical Temperature Spots (Blade - Top Side) Temperature Spot 2 Temperature Spot 1 (48 V to 12 V DC DC) ATCA-7490 Installation and Use (6806800U11F)

  • Page 50: Power Requirements

    Characteristic Value Rated Voltage -48 VDC to -60 VDC Exception in the US and Canada -48 VDC Operating Voltage -39 VDC to -72 VDC Exception in the US and Canada -39 VDC to -60 VDC ATCA-7490 Installation and Use (6806800U11F)

  • Page 51: Table 2-3 Power Consumption Of Atca-7490 With And Without Rtm

    The following table provides information about the maximum power consumption of ATCA- 7490 equipped with DIMMs, SSDs, and RTM-ATCA-749X. The table also contains power consumption details of the blade without any RTM. Table 2-3 Power Consumption of ATCA-7490 with and without RTM Maximum Power...

  • Page 52: Blade Layout

    Hardware Preparation and Installation Blade Layout The following figure shows the location of components on the ATCA-7490. Figure 2-2 ATCA-7490 Blade Layout J28 DIMM 8 J27 DIMM 7 J26 DIMM 6 J25 DIMM 5 J21 DIMM 1 RTM 12V Power...

  • Page 53: Switch Settings

    Table 2-4 Switch SW1 settings Switch Function Default SW1.1 A2F200 JTAG_SEL strap A2F200 JTAGSEL OFF= JTAG to Fabric (Default) ON= JTAG to CPU-Core SW1.2 BIOS Image Swap Default Image ON= Secondary Image in 16MB device ATCA-7490 Installation and Use (6806800U11F)
  • Page 54 ON = Reset push button disabled Table 2-6 Switch SW3 Settings Switch Function Default SW3.1 Manual "Default SPI Boot Flash" / "Recovery SPI IPMI selects Boot Flash Boot Flash" select enable. ON: SW3.2 selects Boot Flash ATCA-7490 Installation and Use (6806800U11F)

  • Page 55: Installing The Blade Accessories

    Each processor provides four memory channels with two DIMM sockets each. When installing DIMM memory modules, the DIMM sockets that are farthest away on each memory channel from the CPU device need to be populated first. ATCA-7490 Installation and Use (6806800U11F)

  • Page 56: Dimm Sockets

    Only qualified DDR4 DIMMs (Single Ranked or Dual Ranked RDIMM) are allowed; because of the thermal limit or budget of the blade and the high variation of the power consumptions of different DIMM types. For thermal reasons, no 4-rank DIMMs and no dual-Die DIMMs are allowed. ATCA-7490 Installation and Use (6806800U11F)
  • Page 57 Damage of Circuits Electrostatic discharge and incorrect module installation and removal can damage circuits or shorten their life. Before touching the module or electronic components, make sure that you are working in an ESD-safe environment. ATCA-7490 Installation and Use (6806800U11F)

  • Page 58: Ssd Carrier And Mo297 Ssd Modules

    SSDs and the MO297-A compliant SSDs. The SSD module is an accessory kit and is not part of the default ATCA-7490. For more information about SSD kit, refer to ATCA-748X MMOD-SSDKIT Quick Start Guide. The following procedure describes the steps to install/remove the MO297-A compliant SSD module.
  • Page 59 3. Fasten the SSD module to the blade using the screws supplied with the ACC kit. 4. Reinstall the blade into the system as described in Installing and Removing the Blade on page The additional resource (either memory or SATA SSD) will be detected automatically during the boot-up sequence. ATCA-7490 Installation and Use (6806800U11F)

  • Page 60: Installing And Removing The Blade

    4. Reinstall the blade into the system as described in Installing and Removing the Blade on page Installing and Removing the Blade The blade is fully compatible to the AdvancedTCA standard and is designed to be used in AdvancedTCA shelves. ATCA-7490 Installation and Use (6806800U11F)

  • Page 61: Installing The Blade

    The following procedure describes the installation of the blade. It assumes that your system is powered on. If your system is not powered on, you can disregard the blue LED and skip the respective step. In this case, it is purely a mechanical installation. ATCA-7490 Installation and Use (6806800U11F)
  • Page 62 Latch Handle 2. Slide the latch into the release position and pull out the handle outward to unlatch the handle from the faceplate. Do not pull the handle fully outward. ATCA-7490 Installation and Use (6806800U11F)
  • Page 63 If your shelf is powered, as soon as the blade is connected to the backplane power pins, the blue LED is illuminated. ATCA-7490 Installation and Use (6806800U11F)

  • Page 64: Removing The Blade

    Before touching the blade or electronic components, make sure you are working in an ESD-safe environment. Blade Malfunctioning Incorrect blade installation and removal can result in blade malfunctioning. When plugging the blade in or removing it, do not press on the faceplate, instead use the handles. ATCA-7490 Installation and Use (6806800U11F)
  • Page 65 Removing the blade with the blue LED still blinking causes data loss. Wait until the blue LED is permanently illuminated before removing the blade. 3. Remove the faceplate cables, if applicable. 4. Remove the blade from the shelf. ATCA-7490 Installation and Use (6806800U11F)
  • Page 66 Hardware Preparation and Installation ATCA-7490 Installation and Use (6806800U11F)

  • Page 67: Controls, Indicators, And Connectors

    Chapter 3 Controls, Indicators, and Connectors This chapter contains information about the Controls, Indicators, and Connectors associated with the ATCA-7490 blade. Faceplate The following figure illustrates the connectors, controls, and LEDs available on the ATCA-7490 faceplate. Figure 3-1 Faceplate Handle...

  • Page 68: Leds

    Off: No activity U1, U2 Base interface activity is visualized via FPGA LEDs U1 and U2. See also section BIOS LED Usage on page 242. User LED, selectable color via FPGA register. Colors: Red, Green, Amber ATCA-7490 Installation and Use (6806800U11F)

  • Page 69: Reset Button

    You cannot reset the IPMC through this reset button. For more information, refer to Switch Settings on page 3.1.3 Connectors The blade provides the following connectors at its faceplate: 1x Serial (COM1)  2x Ethernet  2x USB 3.0  IPMC Debug Console Connector P9  ATCA-7490 Installation and Use (6806800U11F)

  • Page 70: Serial Interface Connector

    3.1.3.1 Serial Interface Connector Serial line interface #1 of Glue Logic FPGA is available on the ATCA-7490 faceplate. A female RJ45 connector is used for serial line connection. It is of type RJ-45 and corresponds to the physical serial interface port 1. By default, the BIOS maps this interface to the serial interface COM1.

  • Page 71: Ethernet Connector

    The blade provides two USB 3.0 connectors at its faceplate and one USB at RTM (zone 3) interface. The USB connectors at faceplate are compliant to the USB 3.0 standard and correspond to the blade's USB interfaces 3 and 4. The USB at RTM interface is compliant to USB 2.0. ATCA-7490 Installation and Use (6806800U11F)

  • Page 72: Ipmc Debug Console Connector P9

    Attaching a device to the front panel USB ports that exceeds the maximum USB current rating of 900mA for USB 3.0 and 500mA for USB 2.0 ports respectively will result in the ATCA-7490 protecting itself through a controlled board shutdown. 3.1.3.4 IPMC Debug Console Connector P9 P9 provides the IPMC Debug Serial Interface output.The P9 connector is a 3-pin Header with...

  • Page 73: On-Board Connectors

    The MO297 SSD module carrier (Riser card) connects three SATA interfaces of the Intel C612 PCH to three slots of standard MO297 type SSD flash discs. This carries the following types of signals: 3 SATA port (from PCH)  Power supply 5V and 3.3V  ATCA-7490 Installation and Use (6806800U11F)

  • Page 74: Figure 3-6 Location Of Mo297 Ssd Module Connector

    Controls, Indicators, and Connectors The location of the MO297 SSD module carrier or riser card is shown in the following figure. Figure 3-6 Location of MO297 SSD Module Connector MO-297 Carrier ATCA-7490 Installation and Use (6806800U11F)

  • Page 75: Table 3-3 Signal Segment Pinout

    Table 3-3 Signal Segment Pinout Pin Number Function Description mate Differential signal Pair A mate Differential signal Pair B mate Table 3-4 Power Segment Pinout Pin Number Function Not used (3.3V) Not used (3.3V) Not used (3.3V Pre-Charge) ATCA-7490 Installation and Use (6806800U11F)
  • Page 76 Controls, Indicators, and Connectors Table 3-4 Power Segment Pinout (continued) Pin Number Function 5V Pre-Charge Reserved Not used (12V Pre-Charge) Not used (12V) Not used (12V) ATCA-7490 Installation and Use (6806800U11F)

  • Page 77: Advancedtca Backplane Connectors

    AdvancedTCA standard, and are called P10, P20, P22 and P23, P30, P31, P32, P33 and P40. The pinouts of all these connectors are given in this section. Figure 3-8 Location of AdvancedTCA Connectors ZONE 2 (Update Channel) ZONE 2 (Base- and Fabric-IF) ZONE 1 ATCA-7490 Installation and Use (6806800U11F)

  • Page 78: Figure 3-9 P10 Backplane Connector Pinout

    Power feed for the blade (VM48_x_CON and RTN_x_CON)  Power enable (ENABLE_x)  IPMB bus signals (IPMB0_x_yyy)  Geographic address signals (HAx)  Ground signals (SHELF_GND and GND)  Reserved signals  Figure 3-9 P10 Backplane Connector Pinout ATCA-7490 Installation and Use (6806800U11F)

  • Page 79: Figure 3-10 P20 Backplane Connector Pinout - Rows A To D

    The pinouts of P20 and P23 are as follows. Figure 3-10 P20 Backplane Connector Pinout - Rows A to D CLK1A_P CLK1A_M CLK1B_P CLK1B_M RRC_EPL4_TX3_P RRC_EPL4_RX3_P RRC_EPL4_TX3_M RRC_EPL4_RX3_M RRC_EPL4_TX1_P RRC_EPL4_TX1_M RRC_EPL4_RX1_P RRC_EPL4_RX1_M POWERVILLE_GE2_TX_P POWERVILLE_GE2_RX_P POWERVILLE_GE2_TX_N POWERVILLE_GE2_RX_N n.c. ATCA-7490 Installation and Use (6806800U11F)

  • Page 80: Figure

    RRC_EPL4_TX2_M RRC_EPL4_RX2_P RRC_EPL4_RX2_M RRC_EPL4_TX0_P RRC_EPL4_TX0_M RRC_EPL4_RX0_P RRC_EPL4_RX0_M n.c. Figure 3-12 P22 Backplane Connector Pinout - Rows A to D FAB_CH4_TX2_P FAB_CH4_TX2_M FAB_CH4_RX2_P FAB_CH4_RX2_M FAB_CH4_TX0_P FAB_CH4_TX0_M FAB_CH4_RX0_P FAB_CH4_RX0_M FAB_CH3_TX2_P FAB_CH3_TX2_M FAB_CH3_RX2_P FAB_CH3_RX2_M FAB_CH3_TX0_P FAB_CH3_TX0_M FAB_CH3_RX0_P FAB_CH3_RX0_M ATCA-7490 Installation and Use (6806800U11F)

  • Page 81: Figure 3-13 P22 Backplane Connector Pinout - Rows E To H

    P22 Backplane Connector Pinout - Rows E to H FAB_CH4_TX3_P FAB_CH4_RX3_M FAB_CH4_RX3_P FAB_CH4_TX3_M FAB_CH4_TX1_P FAB_CH4_TX1_M FAB_CH4_RX1_P FAB_CH4_RX1_M FAB_CH3_TX3_P FAB_CH3_TX3_M FAB_CH3_RX3_P FAB_CH3_RX3_M FAB_CH3_TX1_P FAB_CH3_TX1_M FAB_CH3_RX1_P FAB_CH3_RX1_M Figure 3-14 P23 Backplane Connector Pinout - Rows A to D ATCA-7490 Installation and Use (6806800U11F)

  • Page 82: Figure 3-15 P23 Backplane Connector Pinout - Rows E To H

    Serial (RS232_x_yyyy)  Serial ATA (SATAx_yyy)  USB (USBxy)  PCI Express (PCIEx_yyy)  IPMI (IPMB1_xxx, ISMB_xxx)  Power (VP12_RTM, V3P3_RTM, VP5_RTM)  General control signals (BD_PRESENTx, RTM_PRSNT_N, RTM_RST_KEY-, RTM_RST-)  ATCA-7490 Installation and Use (6806800U11F)

  • Page 83: Figure 3-16 P30 Backplane Connector Pinout - Rows A To D

    RSVD RSVD _149_SERIAL_RTM_RXD _149_SERIAL_RTM_TXD RTM_PS1_N RTM_ENABLE_N RTM_IPMB_SCL Figure 3-17 P30 Backplane Connector Pinout - Rows E to H _149_RTM_MISO _149_RTM_I2C_CLK _149_RTM_MOSI RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD SATA6G_P3_RX_DP RSVD SATA6G_P3_RX_DN _149_USB_RTM_DP RTM_IPMB_SDA ATCA-7490 Installation and Use (6806800U11F)

  • Page 84: Figure 3-18 P31 Backplane Connector Pinout - Rows A To D

    P31 Backplane Connector Pinout - Rows E to H _149_RTM_I2C_CLK PCIE_CPU1_P3_RX_N<15> PCIE_CPU1_P3_TX_N<14> PCIE_CPU1_P3_TX_P<14> PCIE_CPU1_P3_RX_P<13> PCIE_CPU1_P3_TX_P<12> PCIE_CPU1_P3_RX_N<13> PCIE_CPU1_P3_RX_N<11> PCIE_CPU1_P3_TX_P<10> PCIE_CPU1_P3_TX_N<10> PCIE_CPU1_P3_RX_P<9> PCIE_CPU1_P3_TX_P<8> PCIE_CPU1_P3_RX_N<9> PCIE_CPU1_P3_RX_N<7> PCIE_CPU1_P3_TX_P<6> PCIE_CPU1_P3_TX_N<6> PCIE_CPU1_P3_RX_P<5> PCIE_CPU1_P3_TX_P<4> PCIE_CPU1_P3_RX_N<5> PCIE_CPU1_P3_RX_N<3> PCIE_CPU1_P3_TX_N<2> PCIE_CPU1_P3_TX_P<2> PCIE_CPU1_P3_RX_P<1> PCIE_CPU1_P3_TX_P<0> PCIE_CPU1_P3_RX_N<1> CLK100_RTM_CPU1PORT3CD ATCA-7490 Installation and Use (6806800U11F)

  • Page 85: Figure 3-20 P32 Backplane Connector Pinout - Rows A To D

    P32 Backplane Connector Pinout - Rows E to H PCIE_PORT7_RX_M<0> PCIE_PORT7_TX_P<1> PCIE_PORT7_TX_M<1> PCIE_PORT7_RX_P<2> PCIE_PORT7_TX_P<3> PCIE_PORT7_RX_M<2> PCIE_PORT8_TX_M<1> PCIE_PORT8_RX_M<0> PCIE_PORT8_TX_P<1> PCIE_PORT8_RX_P<2> PCIE_PORT8_RX_M<2> PCIE_PORT8_TX_P<3> PCIE_PORT9_RX_M<0> PCIE_PORT9_TX_P<1> PCIE_PORT9_TX_M<1> PCIE_PORT9_RX_P<2> PCIE_PORT9_TX_P<3> PCIE_PORT9_RX_M<2> PCIE_PORT10_RX_M<0> PCIE_PORT10_TX_M<1> PCIE_PORT10_TX_P<1> PCIE_PORT10_RX_P<2> PCIE_PORT10_TX_P<3> PCIE_PORT10_RX_M<2> CLK100_RTMPCIE9_DN CLK100_RTMPCIE8_DN CLK100_RTMPCIE9_DP ATCA-7490 Installation and Use (6806800U11F)

  • Page 86: Table 3-5 P40 Backplane Connector Pinout

    _147_RTM_RRC_I2C_RST_N _147_RRC_RTM_I2C_CLK RRC_EPL5_TX1_M RRC_EPL5_RX0_M RRC_EPL5_RX0_P RRC_EPL5_TX3_P RRC_EPL5_RX2_P RRC_EPL5_TX3_M RRC_EPL6_TX1_M RRC_EPL6_RX0_P RRC_EPL6_RX0_M RRC_EPL6_TX3_P RRC_EPL6_RX2_P RRC_EPL6_TX3_M RRC_EPL7_TX1_M RRC_EPL7_RX0_M RRC_EPL7_RX0_P RRC_EPL7_TX3_P RRC_EPL7_TX3_M RRC_EPL7_RX2_P RRC_EPL8_TX1_M RRC_EPL8_RX0_P RRC_EPL8_RX0_M RRC_EPL8_TX3_P RRC_EPL8_RX2_P RRC_EPL8_TX3_M RSVD Table 3-5 P40 Backplane Connector Pinout Pin# Signal ATCA-7490 Installation and Use (6806800U11F)
  • Page 87 Controls, Indicators, and Connectors Table 3-5 P40 Backplane Connector Pinout (continued) Pin# Signal RTM_VP12 V3P3_MGMT_RTM\G RTM_VP12 ATCA-7490 Installation and Use (6806800U11F)
  • Page 88 Controls, Indicators, and Connectors ATCA-7490 Installation and Use (6806800U11F)

  • Page 89: Functional Description

    This chapter provides a detailed description about the hardware components available on the ATCA-7490 blade. Block Diagram Figure 4-1 shows the block diagram of ATCA-7490 blade. It depicts how the devices work together and the data paths are used. Figure 4-1 ATCA-7490 Block Diagram...

  • Page 90: Processor

    Functional Description Processor ATCA-7490 provides two Intel Xeon E5-26xxL V4 (Broadwell-EP) server processors as the central processing unit (CPU). Each processor provides 40 PCIe lanes up to Gen3 speeds (8GT/s). The processors are connected with each other through two Intel QuickPath Interconnect point-to-point links capable of up to 9.8 GT/s.

  • Page 91: Platform Controller Hub Intel C612 Wellsburg

    CPU#0 through Intel DMI2.0, PCH I/O-controller connected to DMI2 interface of CPU#0. ATCA-7490 supports Intel Hybrid Clocking Mode through the Intel C612 PCH controller. By default, the Spread Spectrum Clocking (SSC) feature is enabled for the 100MHz CPU and the PCIe clocks, which are provided by the Intel C612 and buffered through DB1900 buffer.

  • Page 92: Pch I/O Controller Features

    SPI Interface (Boot Flash)  LPC/Keyboard Controller Style (KCS) Interface  Up to 10 serial ATA (SATA) controllers 6Gb/s of which four are used on ATCA-7490  Six USB 3.0 and eight PCIe 2.0 interfaces of which 2+2 are used on ATCA-7490 ...

  • Page 93: Intel I350 Quad Gb Ethernet Controller

    Recovery BIOS Flash (SPI 1)  The flash is allocated for storing the binary code of the BIOS. The ATCA-7490 boots from the primary flash SPI 0 under normal circumstances. If booting BIOS from primary flash SPI 0 fails, a hardware mechanism automatically changes the flash device select logic to boot from the recovery flash SPI 1.

  • Page 94: Storage Controller

    ATCA Update Channels An Ethernet Port Logic (EPL) of Intel FM10000 is connected to the ATCA Update channel providing 10G/40G Ethernet. ATCA-7490 provides following mapping for PICMG3.0 Update channels: Update Channel #0: Optional i350 1000Base-KX Interface  Update Channel #1-4: RC EPL Port#4 (either 1x 40GBASE-KR4 or 4x 10GBASE-KR) ...
  • Page 95 Functional Description Table 4-1 P20 Backplane Connector Pinout (continued) Pin# Signal RRC_EPL4_TX3_M RRC_EPL4_RX3_P RRC_EPL4_RX3_M CLK3/AB Not Driven RRC_EPL4_TX1_P RRC_EPL4_TX1_M RRC_EPL4_RX1_P RRC_EPL4_RX1_M RRC_EPL4_TX2_P RRC_EPL4_TX2_M RRC_EPL4_RX2_P RRC_EPL4_RX2_M POWERVILLE_GE2_TX_P POWERVILLE_GE2_TX_N POWERVILLE_GE2_RX_P POWERVILLE_GE2_RX_N RRC_EPL4_TX0_P RRC_EPL4_TX0_M RRC_EPL4_RX0_P RRC_EPL4_RX0_M ATCA-7490 Installation and Use (6806800U11F)

  • Page 96: Mo297 Slimsata Embedded Solid State Disc (Ssd) Carrier/Riser Card

    Intel C612 PCH via a SATA interface. The modular approach consists of a riser card, which provide up to three sockets for SSDs and the MO297-A compliant SSDs. Before the storage solution can be mounted on ATCA-7490, the riser card and the SSDs have to be pre- mounted.

  • Page 97: I2C Bus

    Functional Description 4.10.1 I2C Bus ATCA-7490 contains the IPMC controller Master-Only I2C Bus. It is also called as Private I2C Bus, which is connected to a FRU EEPROM, temperature sensors, and monitoring logic of the Power Input Module (PIM). Figure 4-2...

  • Page 98: Fru Data Serial Idrom

    Master-Only I2C 4.10.2 FRU Data serial IDROM ATCA-7490 contains a 64K Byte IDROM. It contains the FRU data, and board specific information. For example, serial number of the board, MAC addresses of network interfaces, and some additional information. The EEPROM has an I2C interface and is connected to the on- board Private I2C interface of IPMC building block.

  • Page 99: System Event Log Eeprom

    Functional Description 4.10.3 System Event Log EEPROM ATCA-7490 contains a 64KByte System Event Log (SEL) PROM. The EEPROM has an I2C interface and is connected to the on-board Private I2C interface of IPMC building block. The IDROM is assigned to I2C address 0xA2.

  • Page 100: Control Logic

    4.15 Faceplate Serial Interfaces The ATCA-7490 has two serial interfaces. They are fully compliant to industry standard 16550 asynchronous communication controllers. The two Serial line interfaces #1 and #2 are integrated in the Intel DH8900CC PCH and routed to the on-board FPGA, which distributes them to either faceplate, RTM, or IPMC for SOL.

  • Page 101: Ipmc Debug Console

    The IPMC Debug Console IF connection is normally routed to a 3-pin on-board header (RS232) The IPMC Debug monitor terminal output can also be routed to the faceplate. The IPMC Debug Console is also available when the ATCA-7490 Payload is powered off. Table 4-4 IPMC Debug Console Destination Selection SW2.2...

  • Page 102: Usb Interfaces

    Functional Description 4.16 USB Interfaces ATCA-7490 USB 3.0 ports allow data transfers up to 4 Gbit/s (500 MByte/s) and USB 2.0 ports allow data transfers up to 480Mb/s (60 MByte/s). Two USB 3.0 ports are routed to the faceplate and one USB 2.0 port is routed to the RTM. The ports available at the faceplate are routed to a dual stacked connector and these are USB 3.0 compliant.

  • Page 103: Real Time Clock

    Optional power-down backup method uses a Super CAP with a 1 Farad capacity. This  provides 300 hours of RTC/SRAM backup. 4.20 SMBus Intel C612 PCH (Wellsburg) provides six SMBus interfaces. Only four interfaces are used on ATCA-7490 as described in the Table 4-5. Table 4-5 SMBus Interface Device / SMBus...

  • Page 104: Figure 4-3 Smbus Architecture

    Functional Description The following figure shows the ATCA-7490 SMBus architecture. Figure 4-3 SMBus Architecture U223 DB1900 DB600 isol isol Header LM75 Upper LM75 Lower U252 MMA8451 PCH SMBUS (MGMT Domain) IPMB-L1 Intel 612 PCH The following table provides SMBus mapping address details.
  • Page 105 LM75 ATCA-7490 Intel #12 Inlet Temp C612 PCH IPMC Sensor LM75 ATCA-7490 Intel #13 Outlet C612 PCH Temp 48V Power PIM4328 ATCA-7490 Intel Interface Sensor C612 PCH CB1900Z clock ATCA-7490 Intel buffer 9ZX21901BKLF C612 PCH ATCA-7490 Installation and Use (6806800U11F)
  • Page 106 Functional Description ATCA-7490 Installation and Use (6806800U11F)

  • Page 107: Maps And Registers

    For example, LPC: r/w means that the register bit is readable/writable from the LPC interface IPMC: The prefix “IPMC:” signals that the access is restricted to the IPMC I2C interface. For example, IPMC: r/w means that the register bit is readable/writable from IPMC I2C interface ATCA-7490 Installation and Use (6806800U11F)

  • Page 108: Register Decoding

    All LPC I/O accesses to address POSTCODE and the address range REGISTERS and within the address ranges of COM1 or COM2 (only when enabled during Super IO configuration) are decoded by the LPC core. 5.1.1.1.2 LPC Memory Decoding The LPC interface never responds to LPC memory accesses. ATCA-7490 Installation and Use (6806800U11F)

  • Page 109: I2C Register Decoding

    The two 7-segment LED displays are also used for power failure indication. Table 5-5 POST Code Register LPC I/O Address: 0x80 IPMC I2C Address: 0x7F Description Default Access POST codes from host LPC: r/w IPMC: r ATCA-7490 Installation and Use (6806800U11F)

  • Page 110: Super Io Configuration Register

    2. Write 86H to Configuration Index Port. 5.1.3.2 Existing the Configuration State The device exits the Configuration State by the following contiguous sequence: 1. Write 68H to Configuration Index Port. 2. Write 08H to Configuration Index Port. ATCA-7490 Installation and Use (6806800U11F)

  • Page 111: Configuration Mode

    The DATA PORT is then used to access the selected register. These registers are accessible only in the Configuration Mode. Table 5-8 Global Configuration Register Summary Index Address Description 0x07 Super IO Logical Device Number ATCA-7490 Installation and Use (6806800U11F)

  • Page 112: Table 5-9 Super Io Logical Device Number Register

    Table 5-10 Super IO Device Identification Register Index Address: 0x20 Description Default Access Device ID LPC: r Table 5-11 Super IO Device Revision Register Index Address: 0x21 Description Default Access Device Revision 0x01 LPC: r ATCA-7490 Installation and Use (6806800U11F)

  • Page 113: Table 5-12 Super Io Lpc Control Register

    SERIRQ Mode: LPC: r 1: Continuous Mode UART Clock pre-divide LPC: r/w 00: divide by 1 01: divide by 8 10: divide by 26 (CLK_UART is 48 MHz) 11: reserved Reserved LPC: r ATCA-7490 Installation and Use (6806800U11F)

  • Page 114: Table 5-14 Logical Device Configuration Register Summary

    Table 5-15 Logical Device Enable Register Index Address: 0x30 Description Default Access Logical Device Enable: LPC: r/w 0: disabled. Currently selected device is inactive. 1: enabled. The currently selected device is enabled. Reserved LPC: r ATCA-7490 Installation and Use (6806800U11F)

  • Page 115: Table 5-18 Logical Device Common Decode Ranges

    Register 0x61is 0xF8. Table 5-18 below for Common Decode Ranges. Table 5-18 Logical Device Common Decode Ranges IO Address range Description 0x3F8 - 0x3FF COM1 0x2F8 - 0x2FF COM2 0x2E8 - 0x2EF COM3 0x3E8 - 0x3EF COM4 ATCA-7490 Installation and Use (6806800U11F)

  • Page 116: Table 5-19 Logical Device Primary Interrupt Register

    UART event (that means, Modem Status Change, Receiver Line Error Condition, Transmit Data Request, Receiver Data Available or Receiver Time Out) and setting the OUT2 bit in the MCR. ATCA-7490 Installation and Use (6806800U11F)

  • Page 117: Uart1 And Uart2 Register Map

    The state of the Divisor Latch Bit (DLAB), which is the MOST significant bit of the Serial Line Control Register (SCR), affects the selection of certain of the UART registers. The DLAB bit must be set high by the system software to access the Baud Rate Generator Divisor Latches (DLL and DLM). ATCA-7490 Installation and Use (6806800U11F)

  • Page 118: Uart Registers Dlab=0

    FIFO. Table 5-24 Receiver Buffer Register (RBR) if DLAB=0 LPC IO Address: Base Description Default Access Receiver Buffer register (RBR) Undef. LPC: r ATCA-7490 Installation and Use (6806800U11F)

  • Page 119: Table 5-25 Transmitter Holding Register (Thr) If Dlab=0

    Transmitter holding register empty (THRE) interrupt LPC: r/w enable/disable 1: THRE interrupt enabled 0: THRE interrupt disabled Receiver line status interrupt enable/disable LPC: r/w 1: receiver line status interrupt enabled 0: receiver line status interrupt disabled ATCA-7490 Installation and Use (6806800U11F)

  • Page 120: Table 5-27 Uart Interrupt Priorities2

    Modem Status: one or more of the modem input signals has changed state. Table 5-28 Interrupt Identification Register (IIR) LPC IO Address: Base + 2 Description Default Access Interrupt status bit: LPC: r 1: no interrupt pending 0: interrupt pending ATCA-7490 Installation and Use (6806800U11F)

  • Page 121: Table 5-29 Interrupt Identification Register Decode

    0b1100 Character FIFO Mode only: At least 1 character is in Reading the Receiver FIFO or Timeout receiver FIFO and there was no activity for setting RESETRF bit in FCR indication. a time period. register ATCA-7490 Installation and Use (6806800U11F)

  • Page 122: Table 5-30 Fifo Control Register (Fcr)

    1: Bytes in receiver FIFO and counter are reset. Shift register is not reset (bit is self-clearing) 0: No effect Transmit FIFO reset: LPC: w 1: Bytes in receiver FIFO and counter are reset. Shift register is not reset (bit is self-clearing) 0: No effect ATCA-7490 Installation and Use (6806800U11F)

  • Page 123: Table 5-31 Line Control Register (Lcr)

    Stop bit length: LPC: r/w 1: 1.5 stop bits for 5 bit WORD length 1: 2 stop bits for 6, 7, and 8 bit WORD length 0: 1 stop bit for any serial character WORD length ATCA-7490 Installation and Use (6806800U11F)
  • Page 124 Bit 7 must be cleared during a read or write to access the RBR, THR, or IER.: 1: Access to DLL and DLM registers 0: Access to RBR, THR and IER registers ATCA-7490 Installation and Use (6806800U11F)

  • Page 125: Table 5-32 Modem Control Register (Mcr)

    Modem control inputs are disconnected Modem control outputs are internally connected to modem control inputs. Modem control outputs are forced to the inactive (high) levels: 1: Loop back mode activated 0: Normal operation ATCA-7490 Installation and Use (6806800U11F)
  • Page 126 FIFO. If the erroneous byte being received is not at the top of the FIFO, an interrupt is generated only after the previous bytes are read and the erroneous byte is moved to the top of the FIFO. ATCA-7490 Installation and Use (6806800U11F)

  • Page 127: Table 5-33 Line Status Register (Lsr)

    FIFO mode, this error is associated with the particular character in the FIFO to which it applies. This error is revealed to the CPU when its associated character is at the top of the FIFO: 1: Parity error occurred 0: No parity error ATCA-7490 Installation and Use (6806800U11F)
  • Page 128 THR by the CPU. In the FIFO mode, THRE is set when the transmit FIFO is empty; it is cleared when at least one byte is written to the transmit FIFO: 1: THR/Transmit FIFO empty 0: THR/Transmit FIFO contains data ATCA-7490 Installation and Use (6806800U11F)
  • Page 129 Modem Status Register provide change information. Bits 03:00 are set to a logic 1 when a control input from the Modem changes state. They are reset to a logic 0 when the processor reads the Modem Status Register. ATCA-7490 Installation and Use (6806800U11F)

  • Page 130: Table 5-34 Modem Status Register (Msr)

    MCR bit 1 (#). Complement of the data set ready (DSR#) input Ext. LPC: r When the ACE is in the diagnostic test mode (LOOP [MCR4] = 1), this bit is equal to the MCR bit 0 (DTR#). ATCA-7490 Installation and Use (6806800U11F)

  • Page 131: Programmable Baud Rate Generator

    Upon loading either of the divisor latches, a 16-bit baud counter is immediately loaded. This prevents long counts on initial load. Access to the divisor latch can be done with a word write. ATCA-7490 Installation and Use (6806800U11F)

  • Page 132: Table 5-36 Divisor Latch Lsb Register (Dll), If Dlab=1

    Description Default Access Divisor Latch LSB (DLL) Undef. LPC: r/w Table 5-37 Divisor Latch MSB Register (DLM), if DLAB=1 LPC IO Address: Base + 1 Description Default Access Divisor Latch MSB (DLM) Undef. LPC: r/w ATCA-7490 Installation and Use (6806800U11F)

  • Page 133: Fpga Register Mapping

    Table 5-40) 0x03 Serial Redirection Control Register (See, Table 5-41) 0x04 Serial over LAN Control Register (See, Table 5-42) 0x05 Serial Line Routing Register (See, Table 5-43) 0x06 IPMC Power Level Register (See, Table 5-44) ATCA-7490 Installation and Use (6806800U11F)
  • Page 134 DIMM ADR Feature Configuration Register (See, Table 5-63) 0x19 r/w1c IPMC Interrupt Status Register (See, Table 5-64) 0x1A r/w1c DIMM ADR Status Register (See, Table 5-65) 0x1E CPU Control Register (See, Table 5-66) 0x1F S-States Control Register (See, Table 5-67) ATCA-7490 Installation and Use (6806800U11F)
  • Page 135 RTM Interrupt Status Register (See, Table 5-90) 0x50 LED Control Register (See, Table 5-91) 0x52 Spare Signal Status Register (See, Table 5-92) 0x54 CPU Presence Detection Register (See, Table 5-93) 0x57 CPU Error Status Register (See, Table 5-94) ATCA-7490 Installation and Use (6806800U11F)
  • Page 136 5-108) 0x7D LPC Scratch Register (See, Table 5-109) 0x7E IPMC Scratch Register (See, Table 5-110) 0x7F POST Code Register (See, Table 5-5) For LPC I/O address 0x80 is used. See Table 5-5 POST Code Register. ATCA-7490 Installation and Use (6806800U11F)

  • Page 137: Module Identification Register

    Maps and Registers 5.1.6 Module Identification Register The Module Identification Register identifies the ATCA-7490 blade. Table 5-39 Module Identification Register Address Offset: 0x00 Description Default Access 15:0 ATCA-7490 Blade Module Identification 0x7490 5.1.7 Version Register The version register provides the version of the FPGA bit stream. The initial value starts at 0x01 and will be incremented with each new release.

  • Page 138: Serial Over Lan (Sol) Control Register

    SOL over COM1 enable: PWR_GOOD: 0 IPMC: r/w 0: disabled LPC: r 1: enabled. COM1 is forwarded to IMPC SOL over COM2 enable: PWR_GOOD: 0 IPMC: r/w 0: disabled LPC: r 1: enabled. COM2 is forwarded to IMPC ATCA-7490 Installation and Use (6806800U11F)

  • Page 139: Serial Line Routing Register

    0: COM1 to Faceplate and COM2 to RTM. LPC: r 1: COM1 to RTM and COM2 to Faceplate. IPMC_COM_ROUTE_DEBUG PWR_GOOD:0 IPMC: r/w 0: IPMC Serial Debug Interface to 3 Pin Header. LPC: r 1: IPMC Serial Debug Interface to Faceplate. Reserved ATCA-7490 Installation and Use (6806800U11F)

  • Page 140: Ipmc Power Level Register

    The content of the failure registers are also displayed via the seven-segment LED displays. 5.1.13.1 ME Power Failure Registers When an ME failure occurs, the red power failure LED (signal PWR_FAIL_) starts blinking. (The LED is one second ON and one second OFF). ATCA-7490 Installation and Use (6806800U11F)

  • Page 141: Table

    ME is in ME_OFF state. ME_ON: ASW power good lost ME_PWR Timeout. No ASW power good after 45ms. ME_WAIT ASW power good lost ME_WAIT_OFF ASW power good lost Other These values will never occur. ATCA-7490 Installation and Use (6806800U11F)

  • Page 142: Payload Power Failure Registers

    Address Offset: 0x0A Description Default Access Payload Power Failure State. Latched last Payload PWR_GOOD:0 IPMC: r Power state when failure occurred. See Table 5-50. Note: Only valid with Payload Failure (Bit 7) is set. Reserved IPMC: r ATCA-7490 Installation and Use (6806800U11F)

  • Page 143: Table

    Other cause: 12V or 5V aux power failure. VCCIN_ENABL Timeout (debug disabled) after 280ms. VCCIN voltages are not good. Other cause: One or more voltages have failed, which have been already enabled and sampled good. ATCA-7490 Installation and Use (6806800U11F)

  • Page 144: Table

    Address Offset: 0x0B Description Default Access Payload wakeup failure: PWR_GOOD:0 IPMC: r 0: No wakeup issue. Board wakes up within 5s timeout. 1: Wakeup failure. Board does not wake up (SLP_S3_ stays low) within 5s timeout. ATCA-7490 Installation and Use (6806800U11F)

  • Page 145: Table 5-51 Payload Power Failure Cause Register 1

    5V power good failure (signal PWRGD_VP5): PWR_GOOD:0 IPMC: r 0: No 5V power issue. 1: 5V power failure. RRC AVDD power good failure (signal PWR_GOOD:0 IPMC: r PWRGD_RRC_AVDD): 0: No RRC AVDD power issue. 1: RRC AVDD power failure. ATCA-7490 Installation and Use (6806800U11F)

  • Page 146: Table 5-52 Payload Power Failure Cause Register 2

    IPMC: r PWRGD_PVPP_ABCD): 0: No VPP CPU0 power issue. 1: VPP CPU0 power failure. VPP CPU1 power good failure (signal PWR_GOOD:0 IPMC: r PWRGD_PVPP_EFGH): 0: No VPP CPU1 power issue. 1: VPP CPU1 power failure. ATCA-7490 Installation and Use (6806800U11F)

  • Page 147: Table 5-53 Payload Power Failure Cause Register 3

    IPMC: r PWRGD_PVCCIN_CPU0): 0: No VCCIN CPU0 power issue. 1: VCCIN CPU0 power failure. VCCIN CPU1 power good failure (signal PWR_GOOD:0 IPMC: r PWRGD_PVCCIN_CPU1): 0: No VCCIN CPU1 power issue. 1: VCCIN CPU1 power failure. ATCA-7490 Installation and Use (6806800U11F)

  • Page 148: Power Status Register

    1: ARTM power failure. RTM_PWRGD is not valid within ~500ms after IPMC switch on ARTM payload or RTM_PWRGD is deasserted when ARTM is up. Note: Failure flag is cleared, when IPMC disables ARTM payload enable. Reserved IPMC: r ATCA-7490 Installation and Use (6806800U11F)

  • Page 149: Reset Registers

    The same situation will happen if two reset sources go active at the same time. OS should never write to this register. ATCA-7490 Installation and Use (6806800U11F)

  • Page 150: Reset Mask Register

    CPU. A “1” in the register bit indicates that the associated reset is enabled. A “0” indicates that the associated reset source is masked. Table 5-58 Reset Mask Register Address Offset: 0x11 Description Default Access Reserved ATCA-7490 Installation and Use (6806800U11F)

  • Page 151: Bios Ipmc Watchdog Timeout Register

    Table 5-59 BIOS IPMC Watchdog Timeout Register Address Offset: 0x12 Description Default Access BIOS IPMC Watchdog Timeout: PWR_GOOD:0 LPC: r/w1c 1: IPMC Watchdog Timeout occurred IPMC: r BIOS IPMC Pre-Timeout PWR_GOOD:0 LPC: r/w1c 1: IPMC Pre-Timeout occurred IPMC: r Reserved ATCA-7490 Installation and Use (6806800U11F)

  • Page 152: Bios Push Button Enable Register

    The same will happen if two reset sources go active at the same time. BIOS should never write to this register. ATCA-7490 Installation and Use (6806800U11F)

  • Page 153: Os Ipmc Watchdog Timeout Register

    When one of the IPMC Watchdog Timeout bits of IPMC Watchdog Timeout Register is set, the corresponding OS IPMC Watchdog Timeout Register bit is set. The OS clears this status bit by writing one. BIOS should never write to this register. ATCA-7490 Installation and Use (6806800U11F)

  • Page 154: Ipmc Watchdog Timeout Register

    IPMC needs to clear the IPMC watchdog timeout bit to arm IPMC watchdog timeout event recognition. Table 5-63 IPMC Watchdog Timeout Register Address Offset: 0x16 Description Default Access IPMC Watchdog Timeout: PWR_GOOD:0 IPMC: r/w 0: No IPMC Watchdog Timeout 1: IPMC Watchdog Timeout occurred ATCA-7490 Installation and Use (6806800U11F)

  • Page 155: Ipmc Reset Source Register

    1: Reset occurred PB_RST_ face plate push button reset PWR_GOOD:0 IPMC: r/w1c 1: Reset occurred Reserved RTM_PB_RST_ Reset key at RTM PWR_GOOD:0 IPMC: r/w1c 1: Reset occurred Reserved PCH_PLTRST_ reset PWR_GOOD:0 IPMC: r/w1c 1: Reset occurred ATCA-7490 Installation and Use (6806800U11F)

  • Page 156: Ipmc Interrupt Status Register

    IPMC interrupt will always be active and produce infinite IPMC interrupts. Table 5-65 IPMC Interrupt Status Register Address Offset: 0x19 Description Default Access IPMC interrupt status PWR_GOOD:0 IPMC: r/w1c 1: Platform Reset occurred (PCH_PLT_RST_) Reserved ATCA-7490 Installation and Use (6806800U11F)

  • Page 157: 10Dimm Adr Configuration Register

    ADR enable for RTM Push button reset PWR_GOOD:0 LPC: r/w 1: ADR enabled IPMC: r 0: ADR disabled ADR enable for IPMI reset PWR_GOOD:0 LPC: r/w 1: ADR enabled IPMC: r 0: ADR disabled Reserved ATCA-7490 Installation and Use (6806800U11F)

  • Page 158: 11Dimm Adr Status Register

    0: Reset is deasserted. Signal is driven high IPMC: r 1: Reset is asserted. Signal is driven low Control Bit for FABRIC2_PLTRST_: LPC: r/w 0: Reset is deasserted. Signal is driven high IPMC: r 1: Reset is asserted. Signal is driven low ATCA-7490 Installation and Use (6806800U11F)

  • Page 159: Cpu Control Register

    PCH_PSTATE_ pulse generation. Minimum low pulse width is Xμs IPMC: w 0: No action 1: Generate PSTATE low pulse. PCH_RCIN_ pulse generation. Minimum low pulse width is Xμs: IPMC: w 0: No action 1: Generate RCIN low pulse. Reserved ATCA-7490 Installation and Use (6806800U11F)

  • Page 160: S-States Control Register

    Power Button Override Function. PWRBTN low pulse is 5s. IPMC: w 0: No action 1: Generate PWRBTN long low pulse. Forced transition to S5. Reserved 5.1.17 NMI Control Status Registers IPMC can initiate a NMI. Host can identify NMI comes from IPMC. ATCA-7490 Installation and Use (6806800U11F)

  • Page 161: Nmi Generation Register

    5.1.18 Interrupt Control and Status Registers The interrupt status registers indicate events of the interrupt input signals. When an interrupt event occurred, the corresponding status bit is read 1. Writing 1 of the corresponding bit clears the bit. ATCA-7490 Installation and Use (6806800U11F)

  • Page 162: Internal Interrupt Status Register

    Address Offset: 0x22 Description Default Access 3: 0 Telecom CLK_MONITOR_FINISHED interrupt: LPC: r One or more Telecom Clock measurements have finished. Telecom CLK_MONITOR_OUT_OF_RANGE interrupt: LPC: r One or more Telecom Clocks are out of range ATCA-7490 Installation and Use (6806800U11F)

  • Page 163: Telecom Interrupt Control Register

    RTM interrupt sources Ext. LPC: r 0: RTM_SPI_MISO is high. No RTM interrupt. 1: RTM_SPI_MISO is low. One or more RTM interrupt sources are active. When RTM SPI Master face is active the current level is latched. ATCA-7490 Installation and Use (6806800U11F)

  • Page 164: Interrupt Mask And Map Registers

    Table 5-77 Address Map of Interrupt Mask and Map Registers Address Offset of Interrupt Source(s) Description Interrupt Mask IPMC to Host IPMC signals interrupt 0x25 Interrupt Telecom Interrupt Telecom Interrupt. 0x26 RTM_SPI_MISO RTM interrupt sources 0x27 ATCA-7490 Installation and Use (6806800U11F)

  • Page 165: Table

    0x12: Frame number 18. INTA_ 0x13: Frame number 19. INTB_ 0x14: Frame number 20. INTC_ 0x15: Frame number 21. INTD_ 0x16 - 0x1F: Frame number 22-31. IRQ Frame Number not valid. Value is ignored. Reserved ATCA-7490 Installation and Use (6806800U11F)

  • Page 166: Pci Express Hot Plug I2C Io Expander Registers

    Ext. Power LED on the baseboard. For a precise definition refer to PCI Express Base Specification, Revision 3.0. PWREN# Output Output signal allowing software to Ext. enable or disable power to a PCI Express slot. ATCA-7490 Installation and Use (6806800U11F)
  • Page 167 A retention latch is used on the platform to mechanically hold the card in place. Refer to PCI Express Server/Workstation Module Electromechanical Spec Rev 1.0 for details of the timing requirements of this pin output. ATCA-7490 Installation and Use (6806800U11F)

  • Page 168: Pca9555 Internal Register Access

    Description Default Access Content of PCA9555 register. 5.1.20 Flash Status and Selection Registers The flash status register indicates the actual status of the mechanical switches SW1.3 (Signal BOOT_TSOP), SW3.1 (Signal BOOT_SEL_EN_) and SW3.2 (Signal BOOT_DEFAULT). ATCA-7490 Installation and Use (6806800U11F)

  • Page 169: Table 5-82 Flash Status Register

    1: Selects Recover Boot SPI Flash. TARGET_BOOT_SELECT. Target Boot Flash Selection. PWR_GOOD: LPC: r 0: Selects Default Boot SPI Flash IPMC: r/w 1: Selects Recovery Boot SPI Flash Note: New flash selection valid with next platform reset. ATCA-7490 Installation and Use (6806800U11F)

  • Page 170: Pch Output Enable Register

    SPI master protocol. The signal, RTM_SPI_MISO is also used to signal an ARTM interrupt to the base board. See Table 5-90. At the moment, there is no ARTM with an SPI interface defined. ATCA-7490 Installation and Use (6806800U11F)

  • Page 171: Table 5-84 Rtm Spi Address/Command Register

    A write access to the RTM SPI Address/Command Register with the Command Bit 1 (Read) starts a SPI read transaction. This contains the data read from the SPI device. Table 5-86 RTM SPI Read Register Address Offset: 0x43 Description Default Access RTM SPI read data LPC: r ATCA-7490 Installation and Use (6806800U11F)

  • Page 172: Update Channel Equalization Control Register

    Table 5-89 RTM Status Register Address Offset: 0x4B Description Default Access RTM power good status: Ext: RTM_PWRGD IPCM: r 0: RTM power not stable or RTM not powered 1: RTM power good Reserved IPCM: r ATCA-7490 Installation and Use (6806800U11F)

  • Page 173: Led Status And Control Register

    0: LED_USER1_ is driven high. LED off 1: LED_USER1 is driven low. LED on Control user LED output Signal LED_USER2_: 00: LED_USER2_ is driven high. LED off 01: LED_USER2 is driven low. LED on Reserved ATCA-7490 Installation and Use (6806800U11F)

  • Page 174: Spare Signals Status Registers

    Ext. CPU0_SKTOCC_) 0: CPU present in socket 1: CPU not present. Socket is empty CPU1 Presence Detection (Status of signal Ext. CPU1_SKTOCC_) 0: CPU present in socket 1: CPU not present. Socket is empty Reserved ATCA-7490 Installation and Use (6806800U11F)

  • Page 175: Cpu Error Status Register

    MHz. Up to 4 different clock inputs may be monitored. See table below. Table 5-95 Supervised Telecom Clocks Reference List Number Name Description SYSCLK_IN_CLK1A CLK1A from backplane SYSCLK_IN_CLK1B CLK1B from backplane SYSCLK_IN_CLK2A CLK2A from backplane SYSCLK_IN_CLK2B CLK2B from backplane ATCA-7490 Installation and Use (6806800U11F)

  • Page 176: Table 5-96 Telecom Clock Monitor Control Register

    Table 5-97 Telecom Clock Monitor Status Register Address: 0x61 Description Default Access Result available for supervised Telecom Clock 0 to 3. LPC: r/w1c Corresponding bit is set when measurement has finished. Clearing bit triggers new measurement. Reserved ATCA-7490 Installation and Use (6806800U11F)

  • Page 177: Table 5-98 Telecom Clock Monitor Out Of Range Register

    Address: 0x63 Description Default Access Select supervised Telecom Clocks. See Table 5-95 Supervised LPC: r/w Telecom Clocks Reference List: 0-3: Select corresponding clock. Reserved The following tables refer to the clock selected with Table 5-99. ATCA-7490 Installation and Use (6806800U11F)

  • Page 178: Table 5-100 Telecom Clock Monitor Time Base Register

    6: Period Counter incremented with each 64th master clock 7: Period Counter incremented with each 128th master clock 8: Period Counter incremented with each 256th master clock 9 and all others: Period Counter incremented with each 512th master clock Reserved ATCA-7490 Installation and Use (6806800U11F)

  • Page 179: Table 5-101 Telecom Clock Monitor Frequency/Period Register

    Clock Monitor Status Register is set. Table 5-102 Telecom Clock Monitor Lower Limit Register Address: 0x67 -0x68 Description Default Access 15:0 Lower Limit for supervised Telecom Clock: LPC: r/w Used by Table 5-98 Telecom Clock Monitor Out of Range Register. ATCA-7490 Installation and Use (6806800U11F)

  • Page 180: Bios Version Registers

    Description Default Access BIOS Version bits 8 to 15 LPC: r/w IPMC: r Table 5-106 BIOS Version Register 3 Address Offset: 0x76 Description Default Access BIOS Version bits 16 to 23 LPC: r/w IPMC: r ATCA-7490 Installation and Use (6806800U11F)

  • Page 181: Ipmc Bios Communication Registers

    Address Offset: 0x7C Description Default Access IPMC BIOS Communication bits PWR_GOOD:0 LPC: r/w IPMC: r/w 5.1.32 Scratch Registers Table 5-110 LPC Scratch Register Address Offset: 0x7D Description Default Access LPC Scratch bits. PWR_GOOD:0 LPC: r/w IPMC: r ATCA-7490 Installation and Use (6806800U11F)

  • Page 182: Table 5-111 Ipmc Scratch Register

    Maps and Registers Table 5-111 IPMC Scratch Register Address Offset: 0x7E Description Default Access IPMC Scratch bits. PWR_GOOD:0 IPMC: r/w LPC: r ATCA-7490 Installation and Use (6806800U11F)

  • Page 183: Bios

    The BIOS setup program is required to configure the blade hardware. This configuration is necessary for operating the blade and connected peripherals. The configuration data are stored in the same flash device from which the board boots. ATCA-7490 Installation and Use (6806800U11F)

  • Page 184: Accessing The Blade Using The Serial Console Redirection

    Terminal emulation programs such as TeraTermPro or Putty can be used. 6.1.2 Default Access Parameters By default, the blade can be accessed using the serial interface COM1. By default, this interface is accessible using an RJ-45 connector at the blade's faceplate. ATCA-7490 Installation and Use (6806800U11F)

  • Page 185: Connecting To The Blade

    3. Connect the NULL-modem cable to COM port of the blade. 4. Start up the blade. Changing Configuration Settings When the system is switched on or rebooted, the presence and functionality of the system components is tested by Power-On Self-Test (POST). ATCA-7490 Installation and Use (6806800U11F)
  • Page 186 In order to navigate in setup, use the arrow keys on the keyboard to highlight items on the menu. All other navigation possibilities are shown at the bottom of the menu. Additionally, an item-specific help is displayed on the right side of the window. ATCA-7490 Installation and Use (6806800U11F)

  • Page 187: Boot Support

    Legacy and UEFI Boot is enabled. With the Boot Priority option, you can determine whether UEFI devices or legacy devices are placed first in the boot order list. Additionally with the setup option PXE Boot capability the type of network boot can be selected between legacy and UEFI. ATCA-7490 Installation and Use (6806800U11F)

  • Page 188: Supported Boot Devices

    By boot selection menu, to select any device for the next boot-up procedure only  By changing the bootorder parameter of IPMI Bootparameter. For more information, refer  to sections IPMI Boot Parameter on page 202 System Boot Options Parameter #100 on page 265. ATCA-7490 Installation and Use (6806800U11F)

  • Page 189: Figure 6-2 Boot Device Priority

    If BIOS is not successful at booting from one device, it tries to boot from the next device on the list. When BIOS does not find any bootable device, the board will be restarted by a cold reset. ATCA-7490 Installation and Use (6806800U11F)

  • Page 190: By Boot Menu

    If a selected legacy boot device does not load the operating system, BIOS will reset the blade. If an EFI boot device does not load the operating system, it will return to the Boot Manager. ATCA-7490 Installation and Use (6806800U11F)

  • Page 191: Sata Raid Configuration

    A detailed description of the Intel® Rapid Storage Technology can be found in Intel® Rapid Storage Technology User Guide, August 2011, Revision 1.0 document. ATCA-7490 Installation and Use (6806800U11F)

  • Page 192: Raid Configuration

    BIOS. To enter the configuration menu of the Option ROM, the following key sequence has to be entered on the serial console. <ESC>, <CTRL-I> or <ESC>, <TAB> Figure 6-4 Intel Rapid Store Technology Option ROM prompt ATCA-7490 Installation and Use (6806800U11F)

  • Page 193: Figure 6-5 Intel Rapid Store Technology Option Rom Main Menu

    The first page of the user interface shows the main menu with Disk/Volume Information. Figure 6-5 Intel Rapid Store Technology Option ROM main menu For creating a new RAID volume, select 1. Create RAID Volume. Figure 6-6 Intel Rapid Store Technology Option ROM create volume menu ATCA-7490 Installation and Use (6806800U11F)

  • Page 194: Raid Configuration For Uefi Boot Type

    8. Exit the user interface by selection of the Exit option, and press <Y> key to confirm exit. 6.4.2.3 RAID configuration for UEFI Boot Type For UEIF Boot Type, the Intel Rapid Store Technology EFI-driver is started by the BIOS. The RAID configuration is in this case part of the BIOS setup. ATCA-7490 Installation and Use (6806800U11F)

  • Page 195: Figure 6-7 Device Manager

    1. Enter the Boot Menu/Front Page by pressing the <F4> key. 2. Select Device Manager from the Boot Menu. Figure 6-7 Device Manager Enter the Intel RSTe SATA Controller device. The first page of the user interface shows the main menu with Disk/Volume Information. ATCA-7490 Installation and Use (6806800U11F)

  • Page 196: Figure 6-8 Intel Rapid Store Technology Main Menu

    BIOS Figure 6-8 Intel Rapid Store Technology main menu For creating a new RAID volume, select Create RAID Volume. The following screen is displayed. Figure 6-9 Intel Rapid Store Technology create volume menu ATCA-7490 Installation and Use (6806800U11F)

  • Page 197: Iscsi Boot

    2. Select Device Manager from the Boot Menu. 3. Select the iSCSI Configuration Menu. 4. Enter an iSCSI Initiator Name. 5. Add one or more iSCSI Attempts. 6. Save the iSCSI configuration with F10 key. ATCA-7490 Installation and Use (6806800U11F)

  • Page 198: Table 6-1 Iscsi Configuration Menu

    ISCSI Initiator Name The worldwide unique name of the iSCSI Initiator. Only IQN format is accepted. Add Attempt Add an iSCSI Attempt Delete Attempts Delete an iSCSI Attempt Change Attempt Order Change the order of iSCSI Attempts ATCA-7490 Installation and Use (6806800U11F)
  • Page 199 BIOS Add an ISCSI Attempt ATCA-7490 Installation and Use (6806800U11F)

  • Page 200: Table 6-2 Add An Iscsi Attempt Menu

    MAC address. Only the last 3 bytes are configurable. Example: Update 0ABBCCDDEEFF to 0ABBCCF07901 by inputting F07901 Enable DHCP Disabled/Ena Enable or disable DHCP bled Initiator IP Address Use to set initiator IP address in dotted-decimal notation. ATCA-7490 Installation and Use (6806800U11F)
  • Page 201 Use to set the CHAP secret password. The secret length range is 12 to 16 bytes. Save Changes Save Changes. The system must be rebooted manually for changes to take place. Back to Previous Page Back to Previous Page ATCA-7490 Installation and Use (6806800U11F)

  • Page 202: Ipmi Boot Parameter

    BIOS setup parameter and an IPMI boot parameter interact. Figure 6-10 IPMI Boot Parameter BIOS Flash 1 BIOS Flash 2 BIOS Parameter Boot Parameter Storage (EEPROM) Default Parameter BIOS USER Read/Write Private I2C DEFUALT IPMC Read Only IPMB-0 To ShMM ATCA-7490 Installation and Use (6806800U11F)

  • Page 203: Bios Setup Configuration

    5. BIOS writes the parameter to the BIOS Parameter in the Flash. 6. BIOS writes the parameter to the IPMI Boot Parameter USER area. BIOS Setup Configuration This section provides information about the various configurations at BIOS setup. ATCA-7490 Installation and Use (6806800U11F)

  • Page 204: Main

    Table 6-3 Main Menu Item Values IPMI Boot parameter Description System Time [15:48:21] Set the Time. Use Enter to switch between Time elements. System Date [Thu 11/11/2014] Set the Date. Use Enter to switch between Date elements. ATCA-7490 Installation and Use (6806800U11F)

  • Page 205: Advanced

    BIOS 6.7.2 Advanced Platform Information This option shows important information about Platform, CPU, QPI, and Memory. Figure 6-12 Platform Information ATCA-7490 Installation and Use (6806800U11F)

  • Page 206: Table 6-4 Advanced >> Rtm Configuration

    Disabled set for this RTM. If disabled, the RTM PCI Express parameter can be set manually. CPU0 PCIe to RTM X4x4x4x4 rtm_cpu0_bif Selects CPU0 PCIe Bifurcation for Width Zone 3 connector (RTM). x4x4x8 x8x4x4 x8x8 ATCA-7490 Installation and Use (6806800U11F)

  • Page 207: Table

    Zone 3 connector (RTM). Gen 1 (2.5 GT/s) Gen 2 (5 GT/s) Gen 3 (8 GT/s) CPU1 PCIe to RTM X4x4x4x4 rtm_cpu1_bif Selects CPU1 PCIe Bifurcation for Width Zone 3 connector (RTM). x4x4x8 x8x4x4 x8x8 ATCA-7490 Installation and Use (6806800U11F)

  • Page 208: Table

    Gen 2 (5 GT/s) Gen 3 (8 GT/s) CPU1 PCIe Port 3D Auto rtm_cpu1_3d Selects CPU1 PCIe Port 3D Speed for Zone 3 connector (RTM). Gen 1 (2.5 GT/s) Gen 2 (5 GT/s) Gen 3 (8 GT/s) ATCA-7490 Installation and Use (6806800U11F)

  • Page 209: Table 6-5 Advanced >> Peripheral Configuration

    Enables/Disables PCI Express Support Single Root I/O Virtualization. PCIe ARI Enabled, Disabled pci_ari Enables/Disables Alternative Routing ID Interpretation (ARI). Pci 64-bit Decode Enabled, Disabled pci_64bit Allows system to support 64- bit BAR for PCI devices. ATCA-7490 Installation and Use (6806800U11F)

  • Page 210: Table 6-6 Advanced >> Peripheral Configuration >> Intel Vt For Directed I/O (Vt-D)

    Figure 6-15 Peripheral Intel VT Configuration Table 6-6 Advanced >> Peripheral Configuration >> Intel VT for Directed I/O (VT-d) Item Values IPMI Boot parameter Description VTd Azalia VCp Enabled, Disabled Enables/Disables Optimizations virtualization optimizations for Azalia. ATCA-7490 Installation and Use (6806800U11F)
  • Page 211 VMM through DMAR ACPI Tables. Interrupt Remapping Enabled, Disabled vtd_ir Enables/Disables VT_D Interrupt Remapping support. Coherency Support Enabled, Disabled Enables/Disables non- (Non-Isoch) isochronous coherency support. Coherency Support Enabled, Disabled Enables/Disables (Isoch) isochronous coherency support. ATCA-7490 Installation and Use (6806800U11F)

  • Page 212: Table 6-7 Advanced >> Sata Configuration

    Enables/Disables SATA Device. Disabled Operation Mode IDE, AHCI, sata_mode Selects the controllers RAID Operation Mode. RAID OROM prompt 2, 4, 6, 8 sata_raidwait Time for delay of SATA RAID delay Seconds Option ROM prompt ATCA-7490 Installation and Use (6806800U11F)

  • Page 213: Figure 6-17 Usb Configuration

    Link Power Management (SALP). SATA Speed Support 1.5 Gb/s, sata_speed Indicates the maximum speed 3.0 Gb/s, the SATA controller can support 6.0 Gb/s on its ports (Only usable in AHCI/RAID mode). USB Configuration Figure 6-17 USB Configuration ATCA-7490 Installation and Use (6806800U11F)

  • Page 214: Table 6-8 Advanced >> Usb Configuration

    Enabled, usb_rtm Enables/Disables USB to RTM. Disabled USB1 3.0 Front Panel Enabled, usb1_3 Enables/Disables USB1 Front Panel USB Disabled 3.0 support. USB2 3.0 Front Panel Enabled, usb2_3 Enables/Disables USB2 Front Panel USB Disabled 3.0 support. ATCA-7490 Installation and Use (6806800U11F)

  • Page 215: Table 6-9 Advanced >> Processor Configuration

    Valid Range: 0 to 3FFE. 3FFF=Disabling all cores: Invalid Socket 1 Core 0 to 3FFE cpu1_dism Core Disable Bitmap Hex Value. Disable 0: Enable all cores. Valid Range: 0 to 3FFE. 3FFF=Disabling all cores: Invalid ATCA-7490 Installation and Use (6806800U11F)
  • Page 216 When disabled, optimizes the system for applications that require high utilization of random memory access. Direct Cache Enabled, cpu_dca Enables/Disables Direct Cache Access Disabled Access (DCA). X2APIC Enabled, cpu_x2apic Enables/Disables extended APIC Disabled support. ATCA-7490 Installation and Use (6806800U11F)

  • Page 217: Table 6-10 Advanced >> Processor Configuration >> Processor Power Management Configuration

    Table 6-10 Advanced >> Processor Configuration >> Processor Power Management Configuration Item Values IPMI Boot parameter Description Enhanced Intel Enabled, cpu_ss Enables/Disables Enhanced Intel SpeedStep Disabled SpeedStep Technology (P-States). Turbo Mode Enabled, cpu_tm Enables/Disables processor Turbo Disabled Mode ATCA-7490 Installation and Use (6806800U11F)
  • Page 218 Enhanced Halt Enabled, cpu_c1e Enables the Enhanced C1E state of the State (C1E) Disabled Report ACPI Cx ACPI C2, cpu_cxacpi Report CPU C3/C6 state to OS as ACPI State ACPI C3 C2 or ACPI C3 state. ATCA-7490 Installation and Use (6806800U11F)

  • Page 219: Table 6-11 Advanced >> Memory Configuration

    Auto, 1333, 1600, mem_speed Maximum Memory Frequency 1867, 2133 Selections in MHz. Halt on Training Enabled, Disabled mem_halt Enables/Disables Halt on Error Memory Training Error. NUMA Enabled, Disabled mem_numa Enables/Disables Non Uniform Memory Access (NUMA). ATCA-7490 Installation and Use (6806800U11F)

  • Page 220: Figure 6-21 Memory Ras Configuration

    IPMI Boot parameter Description Hardware Memory Disabled, Short, mem_test Select Hardware Memory Test Test Long Rank Margin Tool Enabled, Disabled mem_rmt Enable/Disable memory Rank Margin Tool, which tests the DRAM signal margins. Figure 6-21 Memory RAS Configuration ATCA-7490 Installation and Use (6806800U11F)

  • Page 221: Table 6-12 Advanced >> Memory Configuration >> Memory Ras Configuration

    Sparing and Mirroring is not supported. Incase if enabled, Sparing will be selected. Memory Enabled, mem_sparing Enables/Disables Memory Rank Sparing. Rank Sparing Disabled Patrol Scrub Enabled, mem_ps Enables/Disables Patrol Scrub. Disabled Demand Enabled, mem_ds Enables/Disables Demand Scrub. Scrub Disabled ATCA-7490 Installation and Use (6806800U11F)

  • Page 222: Table 6-13 Advanced >> Console Redirection

    Sets Console Redirection terminal VT_UTF8, PC_ANSI type. Baud Rate 115200, 57600, con_br Sets Console Redirection baud rate. 38400, 19200, 9600, 4800, 2400, 1200 Data Bits 7 Bits, 8 Bits con_db Sets Console Redirection data bits. ATCA-7490 Installation and Use (6806800U11F)

  • Page 223: Figure 6-23 Apei Configuration

    Sets Console Redirection stop bits. Flow Control None, XON/XOFF con_fc Sets Console Redirection flow control type. C.R. After Yes, No con_ap Continue Console Redirection after Post POST, when OS is loaded. APEI Configuration Figure 6-23 APEI Configuration ATCA-7490 Installation and Use (6806800U11F)

  • Page 224: Table 6-14 Advanced >> Apei Configuration

    APEI Error Disabled, Inject an error to test APEI Injection MEMORY_CE, feature. MEMORY_UE_NON_ FATAL, MEMORY_UE_FATAL, PCIE_CE, PCIE_UE_NON_FATAL , PCIE_UE_FATAL APEI UEFI UEFI 2.2, UEFI 2.3.1 apei_uefiver UEFI revision of APEI error Revision format. ATCA-7490 Installation and Use (6806800U11F)

  • Page 225: Figure 6-24 Bios Event Log Configuration

    BIOS BIOS Event Log Configuration For more information, refer to BIOS Error Logging on page 239. Figure 6-24 BIOS Event Log Configuration ATCA-7490 Installation and Use (6806800U11F)
  • Page 226 BIOS Figure 6-25 Event Log Viewer ATCA-7490 Installation and Use (6806800U11F)

  • Page 227: Table 6-15 Advanced >> Memory Event Log Viewer

    Table 6-15 Advanced >> Memory Event Log Viewer Item Description Clear Memory Event Log Clears the BIOS stored event log. Clear BMC SEL Event Log Clears the SEL in the IPMC (called as BMC here). ATCA-7490 Installation and Use (6806800U11F)

  • Page 228: Table 6-16 Advanced >> Ipmi Configuration

    The following table contains description about the options that can be configured in IPMI configuration. Table 6-16 Advanced >> IPMI Configuration Item Values IPMI Boot parameter Description IPMI KCS Interrupt Enabled, ipmi_irq Enables/Disables usage of Host Disabled Interface (KCS) interrupt. KCS interrupt is hardwired to IRQ 6. ATCA-7490 Installation and Use (6806800U11F)
  • Page 229 Shows Sensor Data Records (SDR). Lists all SDR information provided by the IPMC. Execute IPMI Executes IPMI Utility for debugging Debug Utility purpose only. Not all commands of this utility are supported by the IPMC. ATCA-7490 Installation and Use (6806800U11F)

  • Page 230: Security

    The following table contains information about the options available for Security configuration. Table 6-17 Security Item Values IPMI Boot parameter Description No Operation, tpm_operation Enables/Disables TPM Function. This Operation Disable and option will automatically return to Deactivate, No-Operation. Enable and Activate ATCA-7490 Installation and Use (6806800U11F)

  • Page 231: Boot

    Values IPMI Boot parameter Description Set Supervisor Install or Change the password. The Password length of password must be greater than one character. 6.7.4 Boot Figure 6-29 shows the Boot menu options. Figure 6-29 Boot ATCA-7490 Installation and Use (6806800U11F)
  • Page 232 RTM SAS Boot is required. USB Boot Enabled, boot_usb Disables/Enables booting from USB Disabled port devices. Info Screen 0 .. 10 info_tmout The number of seconds that the Timeout firmware will wait for <F2> key. ATCA-7490 Installation and Use (6806800U11F)
  • Page 233 Use '+' and '-' keys to move the devices up or down. With the '!' key, a boot device can be enabled or disabled. If the boot entry shows '!' as first character, this boot entry is disabled. ATCA-7490 Installation and Use (6806800U11F)

  • Page 234: Figure 6-31 Legacy Boot Order

    Use '+' and '-' keys to move the devices up or down. With the '!' key, a boot device can be enabled or disabled. If the boot entry shows '!' as first character, this boot entry is disabled. ATCA-7490 Installation and Use (6806800U11F)

  • Page 235: Exit

    Saves the changes made and then exits the system. Save Change Without Exit Saves the changes without exiting the system. Exit Discarding Changes Exits the system without saving the changes. Load Defaults Loads default Settings. ATCA-7490 Installation and Use (6806800U11F)

  • Page 236: Uefi Secure Boot

    2. Press F4 key during boot process to enter Boot menu. 3. In the Boot menu, select the Administer Secure Boot and press Enter. BIOS restarts the board and enter the Administer Secure Boot menu automatically. ATCA-7490 Installation and Use (6806800U11F)

  • Page 237: Restoring Bios Default Settings

    2. Set the on-board switch SW3-4 to ON. Switch Settings on page 53, for the exact location of SW3. 3. Install and power up the blade. 4. Wait until the blade has completely booted and is up and running. ATCA-7490 Installation and Use (6806800U11F)

  • Page 238: Ipmi Support

    5. Remove the blade from the system again. 6. Set switch SW3-4 to OFF. Now the BIOS default settings are restored. 6.10 IPMI Support The ATCA-7490 BIOS provides the following IPMI support: Sets initial timestamp for IPMI SEL events.  Sends Boot Initiated event.

  • Page 239: Bios Error Logging

    - Memory Error Limit Reached - Correctable ECC logging limit reached Uncorrectable: Sensor: Memory, Offset 01h - Uncorrectable ECC Memory Error PCI PERR Sensor: Critical Interrupt, Offset 04h PCI PERR PCI SERR Sensor: Critical Interrupt, Offset 05h PCI SERR ATCA-7490 Installation and Use (6806800U11F)

  • Page 240: Ipmi Error Logging

    71h Base Network not detected 72h Fabric Network not detected 73h Accelerator Device not detected 74h RTM SAS Controller not detected 75h RTM Network not detected 76h RTM PCI Bridge not detected 80h Front Panel Network reduced PCI performance ATCA-7490 Installation and Use (6806800U11F)
  • Page 241 91h Reboot after a BIOS/POST Watchdog Timeout 92h Reboot after a OS Load Watchdog Timeout 93h Reboot after a SMS/OS Watchdog Timeout 94h Reboot after a OEM Watchdog Timeout A0h RTM detected (unknown) AFh RTM-ATCA-7490 detected ATCA-7490 Installation and Use (6806800U11F)

  • Page 242: Bios Led Usage

    Offset 06h Presence detected Event Data2: 0xFF Event Data3: Description Sequential DIMM number (1 to 8) CPU Socket (1 to 2) Figure "ATCA-7490 Blade Layout" on page 52 for DIMM naming convention. Critical Interrupt (13h) Offset 04h PCI PERR Offset 05h PCI SERR...

  • Page 243: Upgrading The Bios

    OS, the reading of the '"POST code" sensor returns no valid status code. For debugging purpose, the POST Codes can be printed to the serial console by setting DIP Switch 3-3 to ON. Table 6-22 BIOS POST Codes POST Code Description Patching CPU microcode ATCA-7490 Installation and Use (6806800U11F)
  • Page 244 Clock Generator Initial Internal Graphic device early initial, PEI_IGDOpRegion HECI Initial Watchdog timer initial Memory Initial for Normal boot Memory Initial for Crisis Recovery Simple Memory test TXT function early initial Start to use Memory ATCA-7490 Installation and Use (6806800U11F)
  • Page 245 Super I/O DXE initial Setup Legacy Region service, DXE_LegacyRegion South Bridge Middle Initial Identify Flash device Fault Tolerant Write verification Variable Service Initial Fail to initial Variable Service MTC Initial CPU Middle Initial Multi-processor Middle Initial ATCA-7490 Installation and Use (6806800U11F)
  • Page 246 Do not support flash part (which is defined in SpiDevice.c) Enter BDS entry Install Hotkey service ASF Initial PCI enumeration PCI resource assign complete PCI enumeration complete Keyboard Controller, Keyboard and Moust initial Video device initial ATCA-7490 Installation and Use (6806800U11F)
  • Page 247 Save S3 resume required data in RAM Last Chipset initial before boot to OS Start to boot Legacy OS Start to boot UEFI OS Prepare to Boot to Legacy OS Send END of POST Message to ME via HECI ATCA-7490 Installation and Use (6806800U11F)
  • Page 248 Get S3 resume required data from memory Start to use memory during S3 resume Set cache for physical memory during S3 resume Start to restore system configuration Restore system configuration stage 1 Restore system configuration stage 2 ATCA-7490 Installation and Use (6806800U11F)
  • Page 249 QPI Initialization: Topology discovery and route calculation QPI Initialization: Program final route QPI Initialization: Program final IO SAD setting QPI Initialization: Protocol layer and other Uncore settings QPI Initialization: Transition links to full speed operation ATCA-7490 Installation and Use (6806800U11F)
  • Page 250 Memory Initialization: JEDEC Init Memory Initialization: Channel Training Memory Initialization: Throttling Init Memory Initialization: BIST Memory Initialization: Init Memory Initialization: DDR Memory Mapping Memory Initialization: RAS Configuration Memory Initialization: Get Margins Memory Initialization: MRC Done ATCA-7490 Installation and Use (6806800U11F)

  • Page 251: Serial Over Lan

    You can configure the SOL parameters via standard IPMI commands or via an open source tool called ipmitool. The ATCA-7490 supports two SOL channels, which are available at their base interfaces. However, only one SOL session is allowed at a time.

  • Page 252: Configuring Using Standard Ipmi Commands

    The ipmicmd is used on the local IPMC and the IP is configured. The ipmicmd is part of the open IPMI package provided in BBS. For more details about BBS, refer to Basic Blade Services Software on ATCA-7490 Programmer’s Reference manual. Sample Procedure To set the IP address: 1.

  • Page 253: Configuration Using Ipmitool

    1. Download the ipmitool tar file from http://ipmitool.sourceforge.net to your blade. 2. Extract the source code. prompt>tar -xjvf ipmitool-<version>.tar.bz2 3. Go to the directory where ipmitool is extracted. prompt>cd <path>/ipmitool-<version> 4. Build the ipmitool. prompt>./configure && make && make install ATCA-7490 Installation and Use (6806800U11F)
  • Page 254 Setting LAN Subnet Mask to 255.255.0.0 The following example shows how to query the LAN parameters that are currently in use for a Potential SOL session for base 1 (channel 1) and base 2 (channel 2): ATCA-7490 Installation and Use (6806800U11F)
  • Page 255 Cipher Suite Priv Max : Not Available root@ATCA7490:~# ipmitool lan print 2 Set in Progress : Set Complete Auth Type Support : Auth Type Enable : Callback: : User: : Operator: : Admin: : OEM: ATCA-7490 Installation and Use (6806800U11F)
  • Page 256 Set in progress : set-complete Enabled : true Force Encryption : false Force Authentication : false Privilege Level : ADMINISTRATOR Character Accumulate Level (ms) : 5 Character Send Threshold Retry Count Retry Interval (ms) : 50 ATCA-7490 Installation and Use (6806800U11F)
  • Page 257 : ADMINISTRATOR Character Accumulate Level (ms) : 5 Character Send Threshold Retry Count Retry Interval (ms) : 50 Volatile Bit Rate (kbps): 115.2 Non-Volatile Bit Rate (kbps): 115.2 Payload Channel: 2 (0x02) Payload Port: 623 ATCA-7490 Installation and Use (6806800U11F)

  • Page 258: Establishing An Sol Session

    4. Configure the network between the ATCA-7490 and your target, which is destined for opening the SOL session, so that the SOL IP address is accessible. 5. Start ATCA-7490 SOL session on your target with the ipmitool and the configured IP address for the ATCA-7490 SOL interface.

  • Page 259: Supported Ipmi Commands

    The system interface commands are supported by blades providing a system interface. Table 8-2 Supported System Interface Commands Command NetFn (Request/Response) Set BMC Global Enables 0x06/0x07 0x2E Get BMC Global Enables 0x06/0x07 0x2F Clear Message Flags 0x06/0x07 0x30 Get Message Flags 0x06/0x07 0x31 ATCA-7490 Installation and Use (6806800U11F)

  • Page 260: Watchdog Commands

    2 sensor. The pre-timeout and power-cycle options are not supported. Table 8-3 Supported Watchdog Commands Command NetFn (Request/Response) Reset Watchdog Timer 0x06/0x07 0x22 Set Watchdog Timer 0x06/0x07 0x24 Get Watchdog Timer 0x06/0x07 0x25 ATCA-7490 Installation and Use (6806800U11F)

  • Page 261: Sel Device Commands

    The following table provides details of supported FRU Inventory commands. Table 8-5 Supported FRU Inventory Commands Command NetFn (Request/Response) Get FRU Inventory Area Info 0x0A/0x0B 0x10 Read FRU Data 0x0A/0x0B 0x11 Write FRU Data 0x0A/0x0B 0x12 ATCA-7490 Installation and Use (6806800U11F)

  • Page 262: Sensor Device Commands

    Get Sensor Event Enable 0x04/0x05 0x29 Get Sensor Event Status 0x04/0x05 0x2B Get Sensor Reading 0x04/0x05 0x2D Get Sensor Type 0x04/0x05 0x2F Set Event Receiver 0x04/0x05 0x00 Get Event Receiver 0x04/0x05 0x01 Platform Event 0x04/0x05 0x02 ATCA-7490 Installation and Use (6806800U11F)

  • Page 263: Chassis Device Commands

    Corresponding Boot Parameter Configurable Boot Property Number Selection between default and backup boot flash as device to boot from Selection between default and backup EEPROM as device where the on-board FPGA loads its configuration stream from ATCA-7490 Installation and Use (6806800U11F)

  • Page 264: Table 8-9 System Boot Options Parameter #96

    0xFF and its state is set to invalid. Its parameter data remains preserved after IPMC power cycles and firmware upgrades. 8.1.7.1.2 System Boot Options Parameter #98 This boot parameter is an Artesyn-specific OEM parameter. ATCA-7490 Installation and Use (6806800U11F)

  • Page 265: Table 8-10 System Boot Options Parameter #98

    The boot parameters in the IPMC storage area have higher priority than the same boot options, which may be configured in the firmware itself, for example, using the setup menu. ATCA-7490 Installation and Use (6806800U11F)

  • Page 266: Figure 8-1 System Boot Options Parameter #100 - Information Flow Overview

    The following figure summarizes the previously explained basic information flow related to the system boot options parameter #100. Figure 8-1 System Boot Options Parameter #100 - Information Flow Overview Boot Parameters IPMI IPMI User Read/Write Boot User Area Firmware Default Area Read Only ATCA-7490 Installation and Use (6806800U11F)

  • Page 267: Table 8-11 System Boot Options - Parameter #100 - Data Format

    The following two tables describe in detail how the request and response data fields need to be filled and interpreted when performing SET and GET accesses. Table 8-12 System Boot Options Parameter #100 - SET Command Usage Byte Description Request Data ATCA-7490 Installation and Use (6806800U11F)

  • Page 268: Table 8-13 System Boot Options Parameter #100 - Get Command Usage

    0xC9: Block selector is outside of the allowed range. Table 8-13 System Boot Options Parameter #100 - GET Command Usage Byte Description Request Data Bit 7: reserved. Set to "0". Bits 6..0: must contain the value: "100", indicating this OEM system boot option. ATCA-7490 Installation and Use (6806800U11F)
  • Page 269 This is supported by HPI, for details refer to the System Management Interface Based on HPI-B User’s Guide related to your system environment. ATCA-7490 Installation and Use (6806800U11F)

  • Page 270: Table 8-14 System Boot Options Parameter #100 - Supported Parameters

    3 connector (RTM). gen1 gen2 gen3 rtm_cpu0_3d Selects CPU0 PCIe Port 3D Speed for Zone auto 3 connector (RTM). gen1 gen2 gen3 rtm_cpu1_bif Selects CPU1 PCIe Bifurcation for Zone 3 X4x4x4x4 connector (RTM). x4x4x8 x8x4x4 x8x8 ATCA-7490 Installation and Use (6806800U11F)
  • Page 271 PCI Express Single Root I/O Virtualization pci_ari Alternative Routing ID nterpretation (ARI) pci_64bit 64-bit BAR support for PCI devices clock_ssc Spread Spectrum Clock Intel Virtualization Technology for Directed I/O (VT-d) vtd_ir VT-d Interrupt Remapping Support ATCA-7490 Installation and Use (6806800U11F)
  • Page 272 USB1 Front Panel USB 3.0 support usb2_3 USB2 Front Panel USB 3.0 support cpu0_dism Core Disable Bitmap Hex Value. Hex Value 0: Enable all cores. 0 to 3FFE Valid Range: 0 to 3FFE. 3FFF=Disabling all cores: Invalid ATCA-7490 Installation and Use (6806800U11F)
  • Page 273 CPU Adjacent Cache Prefetcher cpu_dca CPU Direct Cache Access (DCA) cpu_x2apic CPU Extended APIC support cpu_ss CPU Enhanced Intel SpeedStep Technology (P-States). cpu_tm CPU Turbo Mode cpu_ppw Turbo Mode Performance/Watt tradi optim cpu_cstates CPU C-State support ATCA-7490 Installation and Use (6806800U11F)
  • Page 274 Memory Frequency (MHz) auto 1333 1600 1867 2133 mem_halt Halt on Training Error mem_numa Disable Non Uniform Memory Access (NUMA). mem_test Hardware Memory Test short long mem_ras Memory RAS modes mirror lockstep mem_sparing Memory Rank Sparing ATCA-7490 Installation and Use (6806800U11F)
  • Page 275 19200 38400 57600 115200 con_db Serial console data bits con_par Serial console parity bits con_sb Serial console stop bits con_fc Serial console flow control hard soft con_ap Serial console redirection after POST apei APEI Support ATCA-7490 Installation and Use (6806800U11F)
  • Page 276 IPMI Fail Safe nochange tpm_operation TPM Function. This option will no_operation automatically return to No-Operation. disable_deactivate enable_activate boot_type Boot Type dual legacy uefi boot_priority Determine whether EFI devices or Legacy uefi devices are booted first legacy ATCA-7490 Installation and Use (6806800U11F)

  • Page 277: Table 8-15 Boot Order Devices

    SATA device RTM raid0 SATA RAID device 0 raid1 SATA RAID device 0 raid2 SATA RAID device 0 raid3 SATA RAID device 0 frontnet1 Front Panel Network 1 frontnet2 Front Panel Network 2 basenet1 Base Network 1 ATCA-7490 Installation and Use (6806800U11F)
  • Page 278 EFI Boot from USB device connected to USB2 eifusb3 EFI Boot from USB device connected to USB RTM windows Windows Boot Manager redhat RedHat Linux suse SuSE Linux ubuntu Ubuntu Linux fedora Fedora Linux ATCA-7490 Installation and Use (6806800U11F)

  • Page 279: Lan Device Commands

    Table 8-17 Supported PICMG 3.0 Commands NetFn Command (Request/Response) Comments Get PICMG Properties 0x2C/0x2D 0x00 Get Address Info 0x2C/0x2D 0x01 FRU Control 0x2C/0x2D 0x04 The blade supports the cold reset and graceful reboot options. Get FRU LED Properties 0x2C/0x2D 0x05 ATCA-7490 Installation and Use (6806800U11F)
  • Page 280 Get target upgrade capabilities 0x2C/0x2D 0x2E Get component properties 0x2C/0x2D 0x2F Abort firmware upgrade 0x2C/0x2D 0x30 Initiate upgrade action 0x2C/0x2D 0x31 Upload firmware block 0x2C/0x2D 0x32 Finish firmware upload 0x2C/0x2D 0x33 Get upgrade status 0x2C/0x2D 0x34 ATCA-7490 Installation and Use (6806800U11F)

  • Page 281: Artesyn Specific Commands

    IPMI commands will lead to no or undefined results. Proper handling of these commands is required to write a portable application.  8.3.1 Serial Output Commands Table 8-18 contains supported Serial Output Device commands information. ATCA-7490 Installation and Use (6806800U11F)

  • Page 282: Set Serial Output Command

    0: Faceplate connector 1: Backplane connector All other values are reserved. Note: Only the faceplate connector is supported. No connector on the RTM available. Serial connector instance number. A sequential number that starts from "0". ATCA-7490 Installation and Use (6806800U11F)

  • Page 283: Get Serial Output Command

    MSB of Artesyn Embedded Technologies IANA Enterprise number. 8.3.1.2 Get Serial Output Command The Get Serial Output Command provides a way to determine which serial output source goes to a particular serial port connector. Currently, only BIOS output is supported. ATCA-7490 Installation and Use (6806800U11F)

  • Page 284: Table 8-21 Request Data Of Get Serial Output Command

    Table 8-22 Response Data of Get Serial Output Command Byte Data Field Completion code LSB of Artesyn IANA Enterprise number. Second byte of Artesyn IANA Enterprise number. MSB of Artesyn IANA Enterprise number. Serial output selector ATCA-7490 Installation and Use (6806800U11F)

  • Page 285: Oem Command To Configure Ipmi Features

    This section provides information about the OEM command to configure IPMI features. Table 8-23 Feature Configuration Command Command NetFn (Request/Response) Defined in Set Feature Configuration 0x2E/0x2F Set Feature Configuration Command on page 286 Get Feature 0x2E/0x2F Get Feature Configuration Configuration Command on page 287 ATCA-7490 Installation and Use (6806800U11F)

  • Page 286: Set Feature Configuration

    LSB of Artesyn IANA Enterprise Number. A value of CDh shall be used. 2nd byte of Artesyn IANA Enterprise Number. A value of 65h shall be used. MSB of Artesyn IANA Enterprise Number. A value of 00h shall be used. ATCA-7490 Installation and Use (6806800U11F)

  • Page 287: Get Feature Configuration

    Supported IPMI Commands The following table provides the feature set supported with ATCA-7490. Table 8-25 Feature Selector Assignments Feature Selector Description (3) 03h Handle Debounce (224) E0h FAILSAFE Function Enable/Disable. For details, see Fail Safe Logic on page 349. (225)E1h FAIL PROTECT Function Enable/Disable.

  • Page 288: Pigeon Point Specific Commands

    Table 8-31 on page 293 0x2E/0x2F 0x01 Set Serial Interface Properties Table 8-32 on page 294 0x2E/0x2F 0x02 Get Debug Level Table 8-33 on page 295 0x2E/0x2F 0x03 Set Debug Level Table 8-34 on page 296 0x2E/0x2F 0x04 ATCA-7490 Installation and Use (6806800U11F)
  • Page 289 Table 8-47 on page 305 0x2E/0x2F 0x27 Enable Module Site Table 8-48 on page 307 0x2E/0x2F 0x28 Disable Module Site Table 8-49 on page 307 0x2E/0x2F 0x29 Reset Carrier SDR repository Table 8-50 on page 308 0x2E/0x2F 0x33 ATCA-7490 Installation and Use (6806800U11F)

  • Page 290: Get Status Command

    LSB Byte first: byte 1 = 0A, byte 2 = 40, byte 3 = 00 Response Data Completion Code PPS IANA Private Enterprise ID 0x00400A = 16394 (Pigeon Point Systems) LSB Byte first: byte 2 = 0A, byte 3 = 40, byte 4 = 00 ATCA-7490 Installation and Use (6806800U11F)
  • Page 291 Bits [0:3] Metallic Bus 1 Events These bits indicate pending Metallic Bus 1 requests arrived from the shelf manager: 0: Metallic Bus 1 Query 1: Metallic Bus 1 Release 2: Metallic Bus 1 Force 3: Metallic Bus 1 Free ATCA-7490 Installation and Use (6806800U11F)

  • Page 292: Reset Ipmc Command

    Table 8-30 Reset IPMC Command Description Type Byte Data Field Request Data PPS IANA Private Enterprise ID 0x00400A = 16394 (Pigeon Point Systems) LSB Byte first: byte 1 = 0A, byte 2 = 40, byte 3 = 00 ATCA-7490 Installation and Use (6806800U11F)

  • Page 293: Get Serial Interface Properties Command

    Interface ID 0: Serial Debug Interface Response Data Completion Code PPS IANA Private Enterprise ID 0x00400A = 16394 (Pigeon Point Systems) LSB Byte first: byte 2 = 0A, byte 3 = 40, byte 4 = 00 ATCA-7490 Installation and Use (6806800U11F)

  • Page 294: Set Serial Interface Properties Command

    Data Field Request Data PPS IANA Private Enterprise ID 0x00400A = 16394 (Pigeon Point Systems) LSB Byte first: byte 1 = 0A, byte 2 = 40, byte 3 = 00 Interface ID 0: Serial Debug Interface ATCA-7490 Installation and Use (6806800U11F)

  • Page 295: Get Debug Level Command

    LSB Byte first: byte 1 = 0A, byte 2 = 40, byte 3 = 00 Response Data Completion Code PPS IANA Private Enterprise ID 0x00400A = 16394 (Pigeon Point Systems) LSB Byte first: byte 2 = 0A, byte 3 = 40, byte 4 = 00 ATCA-7490 Installation and Use (6806800U11F)

  • Page 296: Set Debug Level Command

    Table 8-34 Set Debug Level Command Description Type Byte Data Field Request Data PPS IANA Private Enterprise ID 0x00400A = 16394 (Pigeon Point Systems) LSB byte first: byte 1 = 0A, byte 2 = 40, byte 3 = 00 ATCA-7490 Installation and Use (6806800U11F)
  • Page 297 Response Data Completion Code PPS IANA Private Enterprise ID 0x00400A = 16394 (Pigeon Point Systems) LSB byte first: byte 2 = 0A, byte 3 = 40, byte 4 = 00 ATCA-7490 Installation and Use (6806800U11F)

  • Page 298: Get Hardware Address Command

    LSB Byte first: byte 1 = 0A, byte 2 = 40, byte 3 = 00 Hardware Address If set to 00, the ability to override the hardware address is disabled. Note: A hardware address change only takes effect after an IPMC reset. Response Data Completion Code ATCA-7490 Installation and Use (6806800U11F)

  • Page 299: Get Handle Switch Command

    LSB Byte first: byte 2 = 0A, byte 3 = 40, byte 4 = 00 Handle Switch Status 0x00: The handle switch is open. 0x01: The handle switch is closed. 0x02: The handle switch state is read from hardware. ATCA-7490 Installation and Use (6806800U11F)

  • Page 300: Set Handle Switch Command

    LSB Byte first: byte 1 = 0A, byte 2 = 40, byte 3 = 00 Response Data Completion Code PPS IANA Private Enterprise ID 0x00400A = 16394 (Pigeon Point Systems) LSB Byte first: byte 2 = 0A, byte 3 = 40, byte 4 = 00 ATCA-7490 Installation and Use (6806800U11F)

  • Page 301: Set Payload Communication Time-Out Command

    0.1 to 25.5 seconds. Response Data Completion Code PPS IANA Private Enterprise ID 0x00400A = 16394 (Pigeon Point Systems) LSB Byte first: byte 2 = 0A, byte 3 = 40, byte 4 = 00 ATCA-7490 Installation and Use (6806800U11F)

  • Page 302: Enable Payload Control Command

    LSB Byte first: byte 1 = 0A, byte 2 = 40, byte 3 = 00 Response Data Completion Code PPS IANA Private Enterprise ID 0x00400A = 16394 (Pigeon Point Systems) LSB Byte first: byte 2 = 0A, byte 3 = 40, byte 4 = 00 ATCA-7490 Installation and Use (6806800U11F)

  • Page 303: Hang Ipmc Command

    Table 8-44 Graceful Reset Command Description Type Byte Data Field Request Data PPS IANA Private Enterprise ID 0x00400A = 16394 (Pigeon Point Systems) LSB Byte first: byte 1 = 0A, byte 2 = 40, byte 3 = 00 ATCA-7490 Installation and Use (6806800U11F)

  • Page 304: Get Payload Shutdown Time-Out Command

    Completion Code PPS IANA Private Enterprise ID 0x00400A = 16394 (Pigeon Point Systems) LSB Byte first: byte 2 = 0A, byte 3 = 40, byte 4 = 00 Time-Out measured in hundreds of milliseconds, LSB first ATCA-7490 Installation and Use (6806800U11F)

  • Page 305: Set Payload Shutdown Time-Out Command

    LSB Byte first: byte 1 = 0A, byte 2 = 40, byte 3 = 00 Module Site ID Response Data Completion Code PPS IANA Private Enterprise ID 0x00400A = 16394 (Pigeon Point Systems) LSB Byte first: byte 2 = 0A, byte 3 = 40, byte 4 = 00 ATCA-7490 Installation and Use (6806800U11F)
  • Page 306 0: Payload power is bad. 1: Payload power is good. Bit [6] 0: IPMB-L buffer is not attached. 1: IPMB-L buffer is attached. Bit [7] 0: IPMB-L buffer is not ready. 1: IPMB-L buffer is ready. ATCA-7490 Installation and Use (6806800U11F)

  • Page 307: Enable Module Site Command

    LSB Byte first: byte 1 = 0A, byte 2 = 40, byte 3 = 00 Module Site ID Response Data Completion Code PPS IANA Private Enterprise ID 0x00400A = 16394 (Pigeon Point Systems) LSB Byte first: byte 2 = 0A, byte 3 = 40, byte 4 = 00 ATCA-7490 Installation and Use (6806800U11F)

  • Page 308: Reset Carrier Sdr Repository Command

    LSB Byte first: byte 1 = 0A, byte 2 = 40, byte 3 = 00 Response Data Completion Code PPS IANA Private Enterprise ID 0x00400A = 16394 (Pigeon Point Systems) LSB Byte first: byte 2 = 0A, byte 3 = 40, byte 4 = 00 ATCA-7490 Installation and Use (6806800U11F)

  • Page 309: Ipmi Feature Set

    Chapter 9 IPMI Feature Set The ATCA-7490 provides an intelligent hardware management system, as defined in the AdvancedTCA® Base Specification (PICMG® 3.0; AMC.0). This system incorporates two IPMI controllers: An Intelligent Platform Management Controller (IPMC) based on the BMR-A2F-AMCc® ...
  • Page 310 Registers within the Glue Logic FPGA can be accessed by the IPMC via I2C bus. This enhances the capabilities of the IPMC. The Glue Logic FPGA is used to monitor the CPU status, the payload reset cause, the power failure registers, and to control the BIOS boot bank selection. ATCA-7490 Installation and Use (6806800U11F)

  • Page 311: Figure 9-1 Ipmc Block Diagram Of Atca-7490

    IPMI Feature Set A functional block diagram of the ATCA-7490 IPMC/MMC system is shown below. Figure 9-1 IPMC block diagram of ATCA-7490 Front Intel CPU Lattice GLUE (FPGA) 0xFD, 0xFE LM75 TEMP FRU EEPROM 0xA2 LM75 inlet SEL EEPROM 0xA0...

  • Page 312: Firmware Architecture

    The IPMC provides a number of subsidiary threads to serve RTM module discovery and e- keying management. The Application layer can also operate in standalone mode intended to debug the payload without requiring a shelf manager. ATCA-7490 Installation and Use (6806800U11F)

  • Page 313: Firmware Upgrade

    IPMC using an upgrade Agent (for example, fcu or ipmitool ). For detailed information about HPM1 protocol, refer to HPM.1 specification. IPMI bootloader  IPMI firmware  IPMI FRU information   BIOS  FPGA  ATCA-7490 Installation and Use (6806800U11F)

  • Page 314: Ipmi Boot-Loader And Firmware Component

    Also, the boot loader validates new IPMI firmware images. Provided IPMI controller can power up successfully, the current image is made active and the previously active image is made backup. In case power-up fails, the boot loader will automatically recover from crisis and boots from the image. ATCA-7490 Installation and Use (6806800U11F)

  • Page 315: Iap Component

    Instead the blade can be power-cycled gracefully to activate the new firmware. A payload cold reset is not enough to execute a new FPGA component. In this particular case a power cycle is required. ATCA-7490 Installation and Use (6806800U11F)

  • Page 316: Bios Component

    9.2.1.4 BIOS Component The ATCA-7490 provides two SPI flashes for storing two redundant BIOS firmware images; one is called "Active", the other one is "Backup". Due to the fact that the "Active" SPI flash is routed to the Intel CPU always, the IPMC can perform HPM.1 specific firmware upgrades only to the "Backup"...
  • Page 317 #08 Device : RTM HA EE Bank #0 - Active Version: 0.01.00000000 #09 Device : atca-7490-cpu Bank #1 - Active Version: 0.3.00000000 Bank #0 - Rollback Version: 0.1.00000000 Bank marked for next use: #1 ********************[[[[[ REPORT END ]]]]]******************* ATCA-7490 Installation and Use (6806800U11F)

  • Page 318: Firmware Upgrade Tool

    IPMI Feature Set 9.2.3 Firmware Upgrade Tool The primary update mechanism for the ATCA-7490 blade is the FCU tool, which is delivered with the BBS package for the blade. However, the ATCA-7490 blade family also supports ipmitool upgrades with the .

  • Page 319: Updating Ipmitool

    This interface represents the backplane IPMI bus and allows remote firmware upgrade. The count of the simultaneous upgrades is limited because of the bus speed. Examples: From shelf manager:  prompt>ipmitool -t <ipmb_addr> hpm upgrade <file> activate ATCA-7490 Installation and Use (6806800U11F)

  • Page 320: Hpm.2 Specific Firmware Updates

    : Set Complete Auth Type Support Auth Type Enable : Callback : : User : Operator : : Admin : OEM IP Address Source : Static Address IP Address : 172.16.0.221 Subnet Mask : 255.255.0.0 ATCA-7490 Installation and Use (6806800U11F)
  • Page 321 Versions Active Backup File |----|-------------|-----------------|-----------------|------- ----------|----| |* 6|PYLD F/W | 0.05 00000000 | 0.05 00000001 | 0.05 00000001 |100%| |Upload Time: 01:51 | Image Size: 16777217 bytes --------------------------------------------------------------- ---------------- (*) Component requires Payload Cold Reset ATCA-7490 Installation and Use (6806800U11F)

  • Page 322: Sensors

    Performing activation stage: Firmware upgrade procedure successful Sensors This section provides a description of all analog and discrete sensors available on the ATCA-7490. Table 9-2 lists the sensor identification numbers and information regarding the sensor type, name, supported thresholds, assertion and de-assertion information, and a brief description of the sensor purpose.
  • Page 323 IPMI Feature Set Table 9-2 ATCA-7490 Specific Sensors (continued) Event Sensor Event/Reading Event Data Event Data Event Data Threshold/ Assertion Sensor Number Name Sensor Type Type Byte 1 Byte 2 Byte 3 Description Deassertion Rearm Hot Swap Hot Swap Sensor-specific...
  • Page 324 IPMI Feature Set Table 9-2 ATCA-7490 Specific Sensors (continued) Event Sensor Event/Reading Event Data Event Data Event Data Threshold/ Assertion Sensor Number Name Sensor Type Type Byte 1 Byte 2 Byte 3 Description Deassertion Rearm Version Version Sensor-specific Change type...
  • Page 325 IPMI Feature Set Table 9-2 ATCA-7490 Specific Sensors (continued) Event Sensor Event/Reading Event Data Event Data Event Data Threshold/ Assertion Sensor Number Name Sensor Type Type Byte 1 Byte 2 Byte 3 Description Deassertion Rearm RTM 12V Voltage Threshold reading...
  • Page 326 IPMI Feature Set Table 9-2 ATCA-7490 Specific Sensors (continued) Event Sensor Event/Reading Event Data Event Data Event Data Threshold/ Assertion Sensor Number Name Sensor Type Type Byte 1 Byte 2 Byte 3 Description Deassertion Rearm OS Boot OS Boot Sensor-specific...
  • Page 327 IPMI Feature Set Table 9-2 ATCA-7490 Specific Sensors (continued) Event Sensor Event/Reading Event Data Event Data Event Data Threshold/ Assertion Sensor Number Name Sensor Type Type Byte 1 Byte 2 Byte 3 Description Deassertion Rearm Boot System Boot Sensor-specific 0xFF...
  • Page 328 IPMI Feature Set Table 9-2 ATCA-7490 Specific Sensors (continued) Event Sensor Event/Reading Event Data Event Data Event Data Threshold/ Assertion Sensor Number Name Sensor Type Type Byte 1 Byte 2 Byte 3 Description Deassertion Rearm BootBank Sensor-specific 0xFF 0xFF 0x0: Boot Bank A/B...
  • Page 329 IPMI Feature Set Table 9-2 ATCA-7490 Specific Sensors (continued) Event Sensor Event/Reading Event Data Event Data Event Data Threshold/ Assertion Sensor Number Name Sensor Type Type Byte 1 Byte 2 Byte 3 Description Deassertion Rearm PWR Entry Sensor-specific [6] = VOUT_low...
  • Page 330 IPMI Feature Set Table 9-2 ATCA-7490 Specific Sensors (continued) Event Sensor Event/Reading Event Data Event Data Event Data Threshold/ Assertion Sensor Number Name Sensor Type Type Byte 1 Byte 2 Byte 3 Description Deassertion Rearm Reset Source Sensor-specific [7] = IPMC Payload...
  • Page 331 IPMI Feature Set Table 9-2 ATCA-7490 Specific Sensors (continued) Event Sensor Event/Reading Event Data Event Data Event Data Threshold/ Assertion Sensor Number Name Sensor Type Type Byte 1 Byte 2 Byte 3 Description Deassertion Rearm ME Pwr Fail Sensor-specific [2:0]...
  • Page 332 IPMI Feature Set Table 9-2 ATCA-7490 Specific Sensors (continued) Event Sensor Event/Reading Event Data Event Data Event Data Threshold/ Assertion Sensor Number Name Sensor Type Type Byte 1 Byte 2 Byte 3 Description Deassertion Rearm PYLD Pwr Sensor-specific [6:5] 0xFF...
  • Page 333 IPMI Feature Set Table 9-2 ATCA-7490 Specific Sensors (continued) Event Sensor Event/Reading Event Data Event Data Event Data Threshold/ Assertion Sensor Number Name Sensor Type Type Byte 1 Byte 2 Byte 3 Description Deassertion Rearm PYLD Pwr Sensor-specific 0xFF 0xFF...
  • Page 334 IPMI Feature Set Table 9-2 ATCA-7490 Specific Sensors (continued) Event Sensor Event/Reading Event Data Event Data Event Data Threshold/ Assertion Sensor Number Name Sensor Type Type Byte 1 Byte 2 Byte 3 Description Deassertion Rearm DDR7 J17 Temp Threshold reading...
  • Page 335 IPMI Feature Set Table 9-2 ATCA-7490 Specific Sensors (continued) Event Sensor Event/Reading Event Data Event Data Event Data Threshold/ Assertion Sensor Number Name Sensor Type Type Byte 1 Byte 2 Byte 3 Description Deassertion Rearm Switch temp Temp Threshold reading...

  • Page 336: Payload Driven Sensors

    Critical IRQ and Boot Error sensors to enable payload firmware and payload OS to report boot progress/failure via IPMI event messages. The firmware progress sensor implemented with sensor type 0x0F (System Firmware Progress) is used to pass payload boot progress information to the IPMC. ATCA-7490 Installation and Use (6806800U11F)

  • Page 337: Boot Bank Supervision Sensor

    The boot bank information received from this sensor may differ from the boot bank selection performed, in case the boot bank selection has changed after the payload has booted. For details, see BIOS Boot Bank Selection on page 348. ATCA-7490 Installation and Use (6806800U11F)

  • Page 338: Ipmc Post Results Sensor

    0: Hot-swap switch is off 1: Hot-swap switch is on Bit 4 Holdup Switch State 0: Holdup Cap is not connected to -48V Out 1: Holdup Cap is connected to -48V Out Bit 3 Reserved ATCA-7490 Installation and Use (6806800U11F)

  • Page 339: Reset Cause Sensor

    This sensor is used to monitor the last payload reset cause (hard reset, front panel reset or any other reset). The IPMC evaluates the Reset Cause Register within the Glue Logic FPGA. For more information refer to Table "ATCA-7490 Specific Sensors" on page 322. 9.3.7 Voltage and Temperature Sensor There is a selection of voltage and temperature sensors at the front blade.

  • Page 340: Me Power Failure Sensor

    For more information, see Table 5-49. For all possible failing states and their coding, see Table 5-50. When the board is powered via switch SW100.1, the debug mode is enabled, where some timeouts are disabled. ATCA-7490 Installation and Use (6806800U11F)

  • Page 341: Payload Power Failure Cause Sensor

    Master-Only I2CU - Verifies that all expected devices attached to the master-only I2C bus  are accessible. To obtain results of POST, the IPMC supports the IPMI standard command, Get Self Test Results with OEM extensions. This IPMI command can be run at anytime. ATCA-7490 Installation and Use (6806800U11F)

  • Page 342: Ejector Handle De-Bounce

    Configuration on page 286. FRU Inventory The ATCA-7490 implements two intelligent FRUs (IPMC and MMC). Every FRU provides its own FRU information (serial, part, MAC addresses). Depending on the presence of a module, its FRU information is visible or not.

  • Page 343: Mac Address Fru Oem Records

    MAC Address Count (M) (specifying a continuous pool of MAC addresses starting with the MAC address specified in this descriptor) M = 1: this descriptor specifies one MAC address M > 1: this descriptor specifies a pool of MAC addresses with M count ATCA-7490 Installation and Use (6806800U11F)

  • Page 344: Table 9-9 Interface Type Assignments

    The IPMC provides 11 MAC addresses in its FRU information. 4 x fabric interface and 1 MGMT interface implemented with RRC  2 x Base and 2 x front implemented with one Powerville NIC  2 x SOL  ATCA-7490 Installation and Use (6806800U11F)

  • Page 345: Reset And Power Domain

    IPMI Feature Set Reset and Power Domain The ATCA-7490 provides the following FRU instances: FRU #0: front board management and switch  FRU #1: RTM  Each FRU instance can be reset separately. Power Configuration With respect to the product version, the maximum power consumption requested by the IPMC is different.

  • Page 346: Bios Boot Configuration Parameters

    If you are reading from the storage area and you find any of these two values, your software should assume that no boot firmware options have previously been written to the storage area. ATCA-7490 Installation and Use (6806800U11F)

  • Page 347: Asynchronous Event Notification

    9.11 Serial Line Selection The ATCA-7490 provides two serial interfaces from payload. By default, the first is routed to the front connector and the second to the RTM. In addition, there is an IPMC debug interface, which can be routed either to the front or to the RTM (this function is just available if the RTM provides a serial connector at the front).

  • Page 348: Bios Boot Bank Selection

    System Boot Options Commands on page 263. 9.12.1 Boot Bank Sensor The ATCA-7490 provides a Boot Bank Sensor, illustrating from which BIOS Boot Bank the boot firmware has last booted. For details, see Boot Bank Supervision Sensor on page 337.

  • Page 349: Fail Safe Logic

    BMC watchdog expires, the IPMI management controller will swap the boot banks before resetting the CPU. Thus the blade can recover by booting from its redundant boot flash, which contains the old active firmware image, which did work before firmware upgrade. ATCA-7490 Installation and Use (6806800U11F)
  • Page 350 Failsafe count < 3? a System Firmware Hang event to the ShMM Reboot the blade Failsafe in general can recover from scenarios: Missing or defect boot block  Firmware image has a bad checksum  ATCA-7490 Installation and Use (6806800U11F)

  • Page 351: Glue Logic Fpga Flash Selection

    By default, Failsafe is disabled. 9.13 Glue Logic FPGA Flash Selection The ATCA-7490 provides redundant FPGA flashes for both manual and automatic crisis recoveries. The general concept is that there is always an active and a standby SPI flash device. The role of these two devices can be reversed by the IPMC;...

  • Page 352: Boot Bank Sensor

    System Boot Options Commands on page 263. 9.13.1 Boot Bank Sensor The ATCA-7490 provides a Boot Bank Sensor, illustrating from which FPGA Bank the FPGA has booted last. For details, see Boot Bank Supervision Sensor on page 337.
  • Page 353 System Firmware FPGA Done Hang event to the ShMM Both FPGA banks corrupted Set failprotect to FAILED_TWICE Present? Remote Crisis Recovery Mode (M1) FPGA Load Done Swap Boot Bank to protect working image Success ATCA-7490 Installation and Use (6806800U11F)

  • Page 354: Remote Crisis Recover Mode

    The IPMI command, Set/Get System Boot Options together with the OEM parameter #98 can be used to specify the timeout for Graceful Shutdown persistently. For details, see System Boot Options Commands on page 263. By default, Graceful Shutdown persistently value is set to 10 seconds. ATCA-7490 Installation and Use (6806800U11F)

  • Page 355: Local System Event Log (Sel)

    9.15 Local System Event Log (SEL) The ATCA-7490 IPMC supports a local SEL. The local SEL size is configured to hold 1K entries in a circular FIFO buffer. Once the circular buffer is full, the next SEL entry will overwrite the oldest SEL entry in the buffer.
  • Page 356 IPMI Feature Set ATCA-7490 Installation and Use (6806800U11F)

  • Page 357: Replacing The Battery

    Some blade variants contain a on-board battery of type CR2032. Its location is shown in the following figure. A battery-less variant based on SUPERCAP is available on demand. Figure A-1 Location of On-board Battery Battery Location /Goldcap ATCA-7490 Installation and Use (6806800U11F)
  • Page 358 If installing a different battery type other than what is mounted at board delivery may cause data loss. This is because other battery types may be specified for other environments or may have a shorter lifespan. Therefore, only use the same type of lithium battery as is already installed. ATCA-7490 Installation and Use (6806800U11F)
  • Page 359 Removing the battery with a screw driver may damage the PCB or the battery holder. To prevent this damage, do not use a screw driver to remove the battery from its holder. 2. Install the new battery according to the "positive" and "negative" signs. ATCA-7490 Installation and Use (6806800U11F)
  • Page 360 Replacing the Battery ATCA-7490 Installation and Use (6806800U11F)

  • Page 361: Atca-7490 Declassification Procedure

    This section identifies the type, purpose, and procedures to declassify (erase or reinitialize) the non-volatile memory devices to be found on the ATCA-7490 processor card. Users of the procedure are cautioned to verify that the information provided is accurate for its intended use.

  • Page 362: Spi Flash - Processor

    B.1.1 SPI Flash - Processor The ATCA-7490 has two 64MB SPI Flash banks that the CPU uses to store the active and standby BIOS images. The flash device attached to the SPI interface of the Host Bridge requires a special algorithm to access the flash.
  • Page 363 Check with your local sales team to determine the correct image to use. The example below is based on a supplemental BIOS upgrade released after the BBS release). ATCA-737:/root> cd /opt/bladeservices/rom ATCA-7490:/opt/bladeservices/rom/BIOS> fcu -u -f atca- 7490_standard_bios_01_03_0007.fri -datca-7490-cpu ********************[[[[[REPORT BEGIN]]]]]******************** Operation: Upgrade erasing ...100 %...

  • Page 364: Spi Flash - Ipmc

    B.1.2 SPI Flash - IPMC The ATCA-7490 has a Renesas Board Management Controller which contains 128KB of flash split into two different 64KB banks and is used to program the BMC micro-controller. The flash is divided to support an active and a standby image. As with the other processor flash device, it requires a special algorithm to access the flash.

  • Page 365: User Parameters

    Linux. It can store configuration data into an area of the IPMC SPI Flash which is then read during the booting of the ATCA-7490 by the IPMI Base Management Controller and loads those values into memory that is used by the BIOS. The hpmcmd command is be available under BBS for the ATCA-7490, if it is not, ask your local Artesyn Sales team for a copy of the utility.

  • Page 366: Fpga Configuration Flash

    Accidentally writing classified data to these devices is not possible. Declassification of this memory utilizes the fpga_upg utility included with the ATCA-7490 base software. As with the other devices listed previously, the Install_7490_Software.sh automatically will update the microcode sections of these...

  • Page 367: Ipmc I2C Eeprom

    0x9a 0 /tmp/fru_9a In this example the IPMC address of 0x9a assumes the ATCA-7490 is in physical slot 1 of an AXP1440. Be sure to verify the IPMI address of the board with the clia board command to verify the IPMI address for the board.
  • Page 368 They behave like normal solid state hard drives. They can be removed and destroyed or cleared using any standard Linux based software application like dd. The basic procedure to clear this type of device is to: dd if=/dev/zero of=/dev/sda bs=1M ATCA-7490 Installation and Use (6806800U11F)

  • Page 369: Related Documentation

    Table C-1 Artesyn Embedded Technologies - Embedded Computing Publications Document Title Publication Number ATCA-7490 Quick Start Guide 6806800U13 ATCA-7490 Safety Notes Summary 6806800U09 Basic Blade Services Software on ATCA-7490 Programmer’s Reference 6806800U15 RTM-ATCA-749X Installation and Use 6806800U12 ATCA-748X MMOD-SSDKIT Quick Start Guide 6806800T15 ATCA-7490 Installation and Use (6806800U11F)

  • Page 370: Manufacturers' Documents

    Please note that, while these sources have been verified, the information is subject to change without notice. Table C-3 Related Specifications Organization Document Title PICMG ATCA Base Specification R3.0 PICMG Ethernet/Fibre Channel for ATCA Systems Specification 2.0 ATCA-7490 Installation and Use (6806800U11F)
  • Page 372 Artesyn Embedded Technologies, Artesyn and the Artesyn Embedded Technologies logo are trademarks and service marks of Artesyn Embedded Technologies, Inc. All other product or service names are the property of their respective owners. ©2018 Artesyn Embedded Technologies, Inc.

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