ADLINK Technology DAQe-2005 Manuals

Manuals and User Guides for ADLINK Technology DAQe-2005. We have 1 ADLINK Technology DAQe-2005 manual available for free PDF download: User Manual

ADLINK Technology DAQe-2005 User Manual (91 pages)

4-ch, Simultaneous, High Performance Multi-Function Data Acquisition Card

Brand: ADLINK Technology | Category: Storage | Size: 1 MB

Revision History
2
California Proposition 65 Warning
4
Table of Contents
5
List of Tables
7
List of Figures
9
Introduction
11
Features
12
Applications
13
Specifications
14
Table 1-1: -3Db Small Signal Bandwidth
15
Table 1-2: System Noise
16
Table 1-3: CMRR: (DC to 60Hz)
17
Software Support
21
Installation
25
Contents of Package
25
Unpacking
26
Daq/Daqe/Pxi-20Xx Layout
27
Figure 2-1: PCB Layout of the Daq/Daqe-20Xx
27
Figure 2-2: PCB Layout of the PXI-20XX
27
Switch and Jumper Settings
28
Figure 2-3: Board ID SW1 DIP Switch
28
Table 2-1: Board ID SW1 DIP Switch Settings
29
Figure 2-4: Enable Board ID Configuration
30
Figure 2-5: DIO Initial Status (JP4)
31
PCI Configuration
32
Signal Connections
33
Connectors Pin Assignment
33
Table 3-1: 68-Pin VHDCI-Type Pin Assignment
33
Table 3-2: 68-Pin VHDCI-Type Connector Legend
34
Table 3-3: SSI Connector Pin Assignment for Daq/Daqe-20Xx
36
Table 3-4: SSI Connector Pin Assignment on PXI J2
37
Table 3-5: Legend of SSI Connector
37
Analog Input Signal Connection
38
Types of Signal Sources
38
Single-Ended Measurements
38
Figure 3-1: Single-Ended Connections
39
Differential Measurements
39
Figure 3-2: Ground-Referenced Source and Differential Input
39
Figure 3-3: Floating Source and Differential Input
40
Operation Theory
41
A/D Conversion
41
Figure 4-1: Synchronous Digital Inputs Block Diagram
42
Figure 4-2: Synchronous Digital Inputs Timing
42
Table 4-1: Bipolar Analog Input Range and the Output Digital Code on Daq/Daqe/Pxi-2010
43
Table 4-2: Unipolar Analog Input Range and the Output Digital Code on Daq/Daqe/Pxi-2010
43
Table 4-3: Bipolar Analog Input Range and the Output Digital Code on the Daq/Daqe/Pxi-2005/2006
44
Table 4-4: Unipolar Analog Input Range and the Output Digital Code on the Daq/Daqe/Pxi-2005/2006
44
Figure 4-3: Scan Timing
46
Trigger Modes
47
Figure 4-4: Pre-Trigger
48
Figure 4-5: Pre-Trigger Scan Acquisition
48
Figure 4-6: Pre-Trigger with M_Enable = 0 (Trigger Occurs before M Scans)
49
Figure 4-7: Pre-Trigger with M_Enable = 1
49
Figure 4-8: Middle Trigger with M_Enable = 1
51
Figure 4-9: Middle Trigger (Trigger When Scan in Progress)
52
Figure 4-10: Post Trigger
53
Figure 4-11: Delay Trigger
54
Figure 4-12: Post Trigger with Re-Trigger
55
Figure 4-13: Linked List of PCI Address DMA Descriptors
57
D/A Conversion
58
Table 4-5: Bipolar Output Code Table (Vref=10V if Internal Reference Is Selected)
58
Table 4-6: Unipolar Output Code Table (Vref=10V if Internal Reference Is Selected)
59
Software Update
59
Figure 4-14: Typical D/A Timing of Waveform Generation
60
Figure 4-15: Post Trigger Waveform Generation (Assuming the Data in the Data Buffer Are 2V, 4V, 6V, 3V, 0V, -4V, -2V, 4V)
61
Figure 4-16: Delay Trigger Waveform Generation (Assuming the Data in the Data Buffer Are 2V, 4V, 6V, 3V, 0V, -4V, -2V, 4V)
62
Figure 4-17: Re-Triggered Waveform Generation (Assuming the Data in the Data Buffer Are 2V, 4V, 2V, 0V)
62
Figure 4-18: Finite Iterative Waveform Generation with Post-Trigger and Dly2_Counter = 0 (Assuming the Data in the Data Buffer Are 2V, 4V, 2V, 0V)
63
Figure 4-20: Stop Mode I
65
Figure 4-21: Stop Mode II
66
Figure 4-22: Stop Mode III
66
Digital I/O
67
General Purpose Timer/Counter Operation
68
Timer/Counter Functions Basics
68
General Purpose Timer/Counter Modes
69
Figure 4-23: Mode 1 Operation
69
Figure 4-24: Mode 2 Operation
70
Figure 4-25: Mode 3 Operation
70
Figure 4-26: Mode 4 Operation
71
Figure 4-27: Mode 5 Operation
71
Figure 4-28: Mode 6 Operation
72
Figure 4-29: Mode 7 Operation
72
Figure 4-30: Mode 8 Operation
73
Trigger Sources
74
Software-Trigger
74
External Analog Trigger
74
Table 4-7: Analog Trigger SRC1 (EXTATRIG) Ideal Transfer Characteristic
75
Figure 4-31: Analog Trigger Block Diagram
75
Figure 4-32: Below-Low Analog Trigger Condition
76
Figure 4-33: Above-High Analog Trigger Condition
76
Figure 4-34: Inside-Region Analog Trigger Condition
77
Figure 4-35: High-Hysteresis Analog Trigger Condition
77
Figure 4-36: Low-Hysteresis Analog Trigger Condition
78
Figure 4-37: External Digital Trigger
78
User-Controllable Timing Signals
79
Figure 4-38: DAQ Signals Routing
79
Table 4-8: Summary of User-Controllable Timing Signals and the Corresponding Functionalities
80
Auxiliary Function Inputs (AFI)
81
Table 4-9: Auxiliary Function Input Signals and the Corresponding Functionalities
82
System Synchronization Interface
84
Table 4-10: Summary of SSI Timing Signals and the Corresponding Functionalities as the Master or Slave
84
Calibration
87
Loading Calibration Constants
87
Auto-Calibration
88
Saving Calibration Constants
88
Important Safety Instructions
89
Getting Service
91

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