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ADLINK Technology DAQ-2005 User Manual

4-ch, simultaneous, high performance multi-function data acquisition card
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DAQ/DAQe/PXI-
2005/2006/2010
4-ch, Simultaneous, High Performance
Multi-Function Data Acquisition Card
User's Manual
Manual Rev.
Revision Date:
Part No:
1.0
Dec. 29, 2023
50M-12257-1000

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Summary of Contents for ADLINK Technology DAQ-2005

  • Page 1 DAQ/DAQe/PXI- 2005/2006/2010 4-ch, Simultaneous, High Performance Multi-Function Data Acquisition Card User’s Manual Manual Rev. Revision Date: Dec. 29, 2023 Part No: 50M-12257-1000...

  • Page 2: Revision History

    Revision History Revision Release Date Description of Change(s) 2.00 2006-04-20 Previous release PN: 50-11020-1030 Initial release under new part number.  Added 1.4 Software Support.  Added 2.4 Switch and Jumper Settings.  2023-12-29 Added SSI connector pin assignment on ...
  • Page 3 DAQ/DAQe/PXI-20xx Series Preface Copyright © 2023 ADLINK Technology Inc. This document contains proprietary information protected by copy- right. All rights are reserved. No part of this manual may be repro- duced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.

  • Page 4: California Proposition 65 Warning

    California Proposition 65 Warning WARNING: This product can expose you to chemicals including acrylamide, arsenic, benzene, cadmium, Tris(1,3-dichloro-2-propyl)phosphate (TDCPP), 1,4-Diox- ane, formaldehyde, lead, DEHP, styrene, DINP, BBP, PVC, and vinyl materials, which are known to the State of California to cause cancer, and acrylamide, benzene, cadmium, lead, mercury, phthalates, toluene, DEHP, DIDP, DnHP, DBP, BBP, PVC, and vinyl materials, which are known to the State of California to cause...

  • Page 5: Table Of Contents

    DAQ/DAQe/PXI-20xx Series Table of Contents Preface ..................iii List of Tables................. vii List of Figures ................ ix 1 Introduction ................ 1 Features................2 Applications ................. 3 Specifications............... 4 Software Support ............... 11 2 Installation ................ 15 Contents of Package ............15 Unpacking ................
  • Page 6 5 Calibration ................. 77 Loading Calibration Constants........... 77 Auto-calibration ..............78 Saving Calibration Constants..........78 Important Safety Instructions..........79 Getting Service ..............81...

  • Page 7: List Of Tables

    DAQ/DAQe/PXI-20xx Series List of Tables Table 1-1: -3dB small signal bandwidth ........5 Table 1-2: System Noise ............... 6 Table 1-3: CMRR: (DC to 60Hz) ........... 7 Table 2-1: Board ID SW1 DIP Switch Settings ......19 Table 3-1: 68-pin VHDCI-type pin assignment ......23 Table 3-2: 68-pin VHDCI-type Connector Legend ......
  • Page 8 This page intentionally left blank. viii...

  • Page 9: List Of Figures

    DAQ/DAQe/PXI-20xx Series List of Figures Figure 2-1: PCB Layout of the DAQ/DAQe-20xx ....... 17 Figure 2-2: PCB Layout of the PXI-20XX........17 Figure 2-3: Board ID SW1 DIP Switch ........18 Figure 2-4: Enable Board ID Configuration ........ 20 Figure 2-5: DIO Initial Status (JP4) ..........21 Figure 3-1: Single-Ended connections ........
  • Page 10 Figure 4-19: Infinite iterative waveform generation with Post-trigger and DLY2_Counter = 0 (Assuming the data in the data buffer are 2V, 4V, 2V, 0V) ............54 Figure 4-20: Stop mode I (Assuming the data in the data buffer are 2V, 4V, 2V, 0V)........55 Figure 4-21: Stop mode II ............

  • Page 11: Introduction

    DAQ/DAQe/PXI-20xx Series Introduction The DAQ/DAQe/PXI-20xx is an advanced data acquisition card based on the 32-bit PCI architecture. High performance designs and the state-of-the-art technology make this card ideal for data logging and signal analysis ap-plications in medical, process con- trol, etc. Introduction...

  • Page 12: Features

    1.1 Features The DAQ/DAQe/PXI-20xx Advanced Data Acquisition Card pro- vides the following advanced features: 32-bit PCI-Bus, plug and play  4-channel simultaneous differential analog inputs  DAQ/DAQe/PXI-2010: 14-bit Analog input resolution with  sampling rate up to 2MS/s DAQ/DAQe/PXI-2005: 16-bit Analog input resolution with ...

  • Page 13: Applications

    DAQ/DAQe/PXI-20xx Series 1.2 Applications Automotive Testing  Cable Testing  Transient signal measurement   Laboratory Automation  Biotech measurement  Introduction...

  • Page 14: Specifications

    1.3 Specifications Analog Input (AI) Number of channels: 4 differential  A/D converter:  2010: LTC1414 or equivalent  2005: A/D7665 or equivalent  2006: A/D7663 or equivalent  Max sampling rate:  2010: 2MS/s  2005: 500kS/s  2006: 250kS/s ...

  • Page 15: Table 1-1: -3Db Small Signal Bandwidth

    DAQ/DAQe/PXI-20xx Series  -3dB small signal bandwidth: (Typical, 25  Device Input Range Bandwidth (-3dB) Input Range Bandwidth (-3dB) ±10V 1170 kHz 0~10V 1090 kHz ±5V 1050 kHz 0~5V 1020 kHz 2010 ±2.5V 800 kHz 0~2.5V 790 kHz ±1.25V 530 kHz 0~1.25V 530 kHz ±10V...

  • Page 16: Table 1-2: System Noise

    System Noise: (Typical)  Device Input Range System noise Input Range System noise ±10V 0.6 LSBrms 0~10V 0.8 LSBrms ±5V 0.6 LSBrms 0~5V 0.8 LSBrms 2010 ±2.5V 0.6 LSBrms 0~2.5V 0.9 LSBrms ±1.25V 0.6 LSBrms 0~1.25V 0.9 LSBrms ±10V 1.2 LSBrms 0~10V 1.9 LSBrms ±5V...

  • Page 17: Table 1-3: Cmrr: (Dc To 60Hz)

    DAQ/DAQe/PXI-20xx Series CMRR: (DC to 60Hz, Typical)  Device Input Range CMRR Input Range CMRR ±10V 90 dB 0~10V 89 dB ±5V 92 dB 0~5V 92 dB 2010 ±2.5V 95 dB 0~2.5V 94 dB ±1.25V 97 dB 0~1.25V 97 dB ±10V 86 dB 0~10V...
  • Page 18 Resolution: 12 bits  FIFO buffer size:  1k samples per channel when both channels are  enabled for timed DA output, and 2k samples when only one channel is used for timed DA output Data transfers:  Programmed I/O, and bus-mastering DMA with scatter/ ...
  • Page 19 DAQ/DAQe/PXI-20xx Series Output voltage:  Low: VOL=0.5V max; IOL=8mA max.   High: VOH=2.7V min; IOH=400  Synchronous Digital Inputs (SDI, for DAQ/DAQe/PXI-2010  only) Number of channels: 8 digital inputs sampled simultane-  ously with the analog signal input Compatibility: TTL/CMOS ...
  • Page 20 Digital Trigger (D.Trig) Compatibility: TTL/CMOS  Response: Rising or falling edge  Pulse Width: 10ns min  System Synchronous Interface (SSI) Trigger lines: 7  Stability Recommended warm-up time: 15 minutes  Onboard calibration reference:  Level: 5.000V   Temperature coefficient: ±2ppm/ ...

  • Page 21: Software Support

    DAQ/DAQe/PXI-20xx Series 1.4 Software Support ADLINK provides versatile software drivers and packages to suit various user approaches to building a system. Aside from pro- gramming libraries, such as DLLs, for most Windows-based sys- tems, ADLINK also provides drivers for other application environments such as LabVIEW.
  • Page 22 1.4.1 MAPS Core ADLINK MAPS Core is a software package that includes all the device drivers for Windows and a system level management tool called ACE (ADLINK Connection Explorer). With MAPS Core installed, the operating system can identify ADLINK devices and assign the necessary resources for low-level access, such as IO read/write or direct memory access.
  • Page 23 DAQ/DAQe/PXI-20xx Series ADLINK Connection Explorer (ACE) also provides a ready-to-use soft-front panel for digitizer products. Clicking the Launch button in the "Utility" block allows users to control digitizers through the UI and display the acquired waveform/data on the screen. 1.4.2 MAPS/LV, LabVIEW Support Customers who develop their own programs in LabVIEW must install the MAPS/LV software package.
  • Page 24 1.4.3 MAPS/C, C & C++ Support Customers who develop their own programs in C or C++ environ- ments must install the MAPS/C software package. MAPS/C includes all the software components required for developing applications in C/C++, such as header files, a device API library and versatile sample programs for understanding how to manipu- late the device correctly.

  • Page 25: Installation

    DAQ/DAQe/PXI-20xx Series Installation This chapter describes how to install the DAQ/DAQe/PXI-20xx. The contents of the package and unpacking information that you should be aware of are outlined first. 2.1 Contents of Package In addition to this User's Guide, the package should include the following items: DAQ/DAQe/PXI-20xx Multi-function Data Acquisition Card ...

  • Page 26: Unpacking

    2.2 Unpacking Your DAQ/DAQe/PXI-20xx Series card contains electro-static sensitive components that can be easily be damaged by static electricity. Therefore, the card should be handled on a grounded anti-static mat. The operator should be wearing an anti-static wristband, grounded at the same point as the anti-static mat. Inspect the card module carton for obvious damages.

  • Page 27: Daq/Daqe/Pxi-20Xx Layout

    DAQ/DAQe/PXI-20xx Series 2.3 DAQ/DAQe/PXI-20xx Layout Figure 2-1: PCB Layout of the DAQ/DAQe-20xx Figure 2-2: PCB Layout of the PXI-20XX Installation...

  • Page 28: Switch And Jumper Settings

    2.4 Switch and Jumper Settings 2.4.1 Board ID (SW1) The DAQ/DAQe/PXI-20xx Series has a built-in DIP switch (SW1), which is used to define each card’s board ID. When there are mul- tiple cards on the same platform, this board ID switch is useful for identifying each card’s device number.

  • Page 29: Table 2-1: Board Id Sw1 Dip Switch Settings

    DAQ/DAQe/PXI-20xx Series Pin 1 Pin 2 Pin 3 Pin 4 Board ID Table 2-1: Board ID SW1 DIP Switch Settings Installation...

  • Page 30: Figure 2-4: Enable Board Id Configuration

    Board ID configuration is disabled by default. To enable Board ID configuration, install D2K-DASK and launch W2K_D2kUtil.exe in C:\ADLINK\D2K-DASK\Utility\. Select NOTE: NOTE: your Card Type and uncheck Ignore Board ID. See figure below. Figure 2-4: Enable Board ID Configuration Installation...

  • Page 31: Figure 2-5: Dio Initial Status (Jp4)

    DAQ/DAQe/PXI-20xx Series 2.4.2 DIO Initial Status (JP4) The default jumper setting is enabled, making the DIO initial status low by using a 1K ohm resistor poll down to GND. To disable this feature, move the jumper cap as shown in the table below. Disabled Enabled Figure 2-5: DIO Initial Status (JP4)

  • Page 32: Pci Configuration

    2.5 PCI Configuration 1. Plug and Play: As a plug and play component, the card requests an inter- rupt number via its PCI controller. The system BIOS responds with an interrupt assignment based on the card information and on known system parameters. These sys- tem parameters are determined by the installed drivers and the hardware load seen by the system.

  • Page 33: Signal Connections

    DAQ/DAQe/PXI-20xx Series Signal Connections This chapter describes the connectors of the DAQ/DAQe/PXI- 20xx, and the signal connection between the DAQ/DAQe/PXI- 20xx and external devices. 3.1 Connectors Pin Assignment The DAQ/DAQe/PXI-20xx is equipped with one 68-pin VHDCI- type connector (AMP-787254-1). It is used for digital input/output, analog input / output, and timer/counter signals, etc.

  • Page 34: Table 3-2: 68-Pin Vhdci-Type Connector Legend

    AFI1 21 55 AFI0 22 56 23 57 24 58 25 59 26 60 27 61 DGND 28 62 DGND 29 63 30 64 31 65 32 66 33 67 34 68 Table 3-1: 68-pin VHDCI-type pin assignment * SDI for DAQ/DAQe/PXI-2010 only; NC for DAQ/DAQe/PXI-2005/2006 Legend: Pin # Signal Name...
  • Page 35 DAQ/DAQe/PXI-20xx Series Pin # Signal Name Reference Direction Description Source of 15,16 GPTC<0,1>_SRC DGND Input GPTC<0,1> Gate of 17,51 GPTC<0,1>_GATE DGND Input GPTC<0,1> Output of 18,52 GPTC<0,1>_OUT DGND Input GPTC<0,1> Up/Down of 19,53 GPTC<0,1>_UPDOWN DGND Input GPTC<0,1> External TIME- EXTTIMEBASE DGND Input BASE...

  • Page 36: Table 3-3: Ssi Connector Pin Assignment For Daq/Daqe-20Xx

    Pin # Signal Name Reference Direction Description Auxiliary Func- tion Input 0 AFI0 DGND Input (ADCONV, AD_START) Auxiliary Func- tion Input 1 AFI1 DGND Input (DAWR, DA_START) Table 3-2: 68-pin VHDCI-type Connector Legend *PIO means programmable I/O SSI_TIMEBASE DGND SSI_ADCONV DGND SSI_DAWR DGND...

  • Page 37: Table 3-4: Ssi Connector Pin Assignment On Pxi J2

    DAQ/DAQe/PXI-20xx Series SSI Connector Signal Description on PXI J2: Sync. Signal PXI J2 location PXI Trigger Bus SSI_TIMEBASE PXI_TRIG4 SSI_ADCONV PXI_TRIG1 SSI_SCAN_START PXI_TRIG3 SSI_AD_TRIG PXI_TRIG5 SSI_DAWR PXI_TRIG2 SSI_DA_START PXI_TRIG0 SSI_DA_TRIG PXI_TRIG6 Table 3-4: SSI Connector Pin Assignment on PXI J2 Legend: SSI timing signal Functionality...

  • Page 38: Analog Input Signal Connection

    3.2 Analog Input Signal Connection The DAQ/DAQe/PXI-20xx provides 4 differential analog input channels. The analog signal can be converted to digital values by the A/D converter. To avoid ground loops and get more accurate measurements from the A/D conversion, it is quite important to understand the signal source type and how to connect the analog input signals.

  • Page 39: Figure 3-1: Single-Ended Connections

    DAQ/DAQe/PXI-20xx Series Figure 3-1: Single-Ended connections In single-ended configurations, more electrostatic and magnetic noise couples into the single connections than in differential con- figurations. Therefore, the single-ended connection is not recom- mended unless minimal wire connections are necessary. 3.2.3 Differential Measurements Differential Connection Grounded-Reference...

  • Page 40: Figure 3-3: Floating Source And Differential Input

    Differential Connection for Floating Signal Sources Figure 3-3 shows how to connect a floating signal source to DAQ/DAQe/PXI-20xx in differential input mode. For floating signal sources, you need to add a resistor at each channel to provide a bias return path. The resistor value should be about 100 times the equivalent source impedance.

  • Page 41: Operation Theory

    DAQ/DAQe/PXI-20xx Series Operation Theory The operation theory of the functions on the DAQ/DAQe/PXI-20xx is described in this chapter. The functions include the A/D conver- sion, D/A conversion, Digital I/O and General Purpose Counter/ Timer. The operation theory can help you understand how to con- figure and program the DAQ/DAQe/PXI-20xx.

  • Page 42: Figure 4-1: Synchronous Digital Inputs Block Diagram

    4.1.1 DAQ/DAQe/PXI-2010 AI Data Format Synchronous Digital Inputs (for DAQ/DAQe/PXI-2010 only) When each A/D conversion is completed, the 14-bits converted digital data accompanied with 2 bits of SDI<1..0>_X per chan- nel from J5 will be latched into the 16-bit register and data FIFO, as shown in Figure 8 and Figure 9.

  • Page 43: Table 4-1: Bipolar Analog Input Range And The Output Digital Code On Daq/Daqe/Pxi-2010

    DAQ/DAQe/PXI-20xx Series Table 4-1 and 4-2 illustrate the ideal transfer characteristics of var- ious input ranges of DAQ/DAQe/PXI-20xx. The converted digital codes for DAQ/DAQe/PXI-2010 are 14-bit and 2’s complement, and here we present the codes as hexa-decimal numbers. Note that the last 2 bits of the transferred data, which are the synchro- nous digital input (SDI), should be ignored when retrieving the analog data.

  • Page 44: Table 4-3: Bipolar Analog Input Range And The Output Digital Code On The Daq/Daqe/Pxi-2005/2006

    PXI-2005/2006 are 16-bit and direct binary, and here we present the codes as hexadecimal numbers. Description Bipolar Analog Input Range Digital code Full-scale Range ±10V ±5V ±2.5V ±1.25V Least significant bit 305.2uV 152.6uV 76.3uV 38.15uV FSR-1LSB 9.999695V 4.999847V 2.499924V 1.249962V FFFF Midscale +1LSB 305.2uV...
  • Page 45 DAQ/DAQe/PXI-20xx Series version is fully controlled under software. However, it is difficult to control the A/D con-version rate. Specifying Channel, Gain, and Polarity In both the Software Polling and programmable scan acquisi- tion mode, the channel, gain, and polarity for each channel can be specified and selected.

  • Page 46: Figure 4-3: Scan Timing

    Example: (Post-trigger acquisition) SI_counter = 160 PSC_counter = 30 TIMEBASE = Internal clock source Then Scan Interval = 160/40M s = 4 us Total acquisition time = 30 X 4 us = 120 us TIMEBASE clock source In scan acquisition mode, all the A/D conversions start on the output of counters, which use TIMEBASE as the clock source.

  • Page 47: Trigger Modes

    DAQ/DAQe/PXI-20xx Series There are 4 trigger modes to start the scan acquisition, please refer to section 4.1for more details. The data transfer mode is discussed below. The maximum A/D sampling rate is 2MHz for DAQ/  DAQe/PXI-2010, 500kHz for DAQ/DAQe/PXI-2005, 250kHz for DAQ/DAQe/PXI-2006.

  • Page 48: Figure 4-4: Pre-Trigger

    ger event in pre-trigger acquisition. The total stored amount of data = Number of enabled channels * M_counter. Figure 4-4: Pre-trigger (trigger occurs after at least M scans acquired) Note that If the trigger event occurs when a conversion is in progress, the data acquisition won’t stop until this conversion is completed, and the stored M scans of data include the last scan, as illustrated in Fig- ure 4-5, where M_counter = M =3, PSC_counter = 0.

  • Page 49: Figure 4-6: Pre-Trigger With M_Enable = 0 (Trigger Occurs Before M Scans)

    DAQ/DAQe/PXI-20xx Series of data are converted, and it assures the user M scans of data under pre-trigger mode, as illustrated in Figure 4-7. However, if M_enable is set to 0, the trigger signal will be accepted any time, as illustrated in Figure 13. Note that the total amount of stored data will always be equal to the number in the M_counter because the data acquisition won’t stop until a scan is completed.
  • Page 50 The PSC_counter is set to 0 in pre-trigger acquisition mode. NOTE: NOTE: Middle-Trigger Acquisition Use middle-trigger acquisition in applications where you want to collect data before and after a trigger event. The number of scans (M) stored before the trigger is specified in M_counter, while the number of scans (N) after the trigger is specified in PSC_counter.

  • Page 51: Figure 4-8: Middle Trigger With M_Enable = 1

    DAQ/DAQe/PXI-20xx Series Figure 4-8: Middle trigger with M_enable = 1 Operation Theory...

  • Page 52: Figure 4-9: Middle Trigger (Trigger When Scan In Progress)

    If the trigger event occurs when a scan is in progress, the stored N scans of data would include this scan, as illustrated in Figure 4-9. Figure 4-9: Middle trigger (trigger when scan in progress) M_counter defined in Middle-Trigger is different from that of Pre-Trigger.

  • Page 53: Figure 4-10: Post Trigger

    DAQ/DAQe/PXI-20xx Series Post-Trigger Acquisition Use post-trigger acquisition in applications where you want to col- lect data after a trigger event. The number of scans after the trig- ger is specified in PSC_counter, as illustrated in Figure 4-10. The total acquired data length = number of enable-channel * PSC_counter.

  • Page 54: Figure 4-11: Delay Trigger

    Delay Trigger Acquisition Use delay trigger acquisition in applications where you want to delay the data collection after the occurrence of a specified trig- ger event. The delay time is controlled by the value, which is pre-loaded in the Delay_counter (16bit). The counter counts down on the rising edge of the Delay_counter clock source after the trigger condition is met.

  • Page 55: Figure 4-12: Post Trigger With Re-Trigger

    DAQ/DAQe/PXI-20xx Series Post-Trigger or Delay-trigger Acquisition with re-trigger Use post-trigger or delay-trigger acquisition with re-trigger function in ap-plications where you want to collect data after several trigger events. The number of scans after each trigger is specified in PSC_counter, and users could program Retrig_no to specify the re-trigger numbers.
  • Page 56 Bus-mastering DMA Data Transfer In programmable scan acquisition mode, all DAQ/DAQe/PXI series cards supports bus-mastering DMA data transfer. PCI bus-mastering DMA is necessary for high speed DAQ in order to utilize the maximum bus bandwidth. The bus-mastering con- troller controls the PCI bus when it becomes the master. Bus mastering reduces the size of the onboard memory and reduces CPU loading since data is directly transferred to the system memory with no host CPU intervention.

  • Page 57: Figure 4-13: Linked List Of Pci Address Dma Descriptors

    DAQ/DAQe/PXI-20xx Series descriptor. PCI address and PCI dual address cycle support 64-bit addresses which can be mapped into more than 4 GB of the address space. You can allocate many small size memory blocks and chain their associative DMA descriptors altogether by their application programs.

  • Page 58: D/A Conversion

    4.2 D/A Conversion There are 2 channels of 12-bit D/A output available in the DAQ/ DAQe/PXI-20xx. When using D/A converters, users should assign and control the D/A converter reference sources for the D/A oper- ation mode and D/A channels. Users could also select the output polarity: unipolar or bipolar.

  • Page 59: Table 4-6: Unipolar Output Code Table (Vref=10V If Internal Reference Is Selected)

    DAQ/DAQe/PXI-20xx Series Digital Code Analog Output 111111111111 Vref * (4095/4096) 100000000000 Vref * (2048/4096) 000000000001 Vref * (1/4096) 000000000000 Table 4-6: Unipolar output code table (Vref=10V if internal reference is selected) The D/A conversion is initiated by a trigger source. Users must decide how to trigger the D/A conversion.

  • Page 60: Figure 4-14: Typical D/A Timing Of Waveform Generation

    These counters are: UI_counter (24 bits): specify the DA Update Interval = CHUI_counter/TIMEBASE. UC_counter (24 bits): specify the total Update Counts in a single waveform IC_counter (24 bits): specify the Iteration Counts of waveform. DA_DLY1_counter (16 bits): specify the Delay from the trigger to the first update start.

  • Page 61: Figure 4-15: Post Trigger Waveform Generation (Assuming The Data In The Data Buffer Are 2V, 4V, 6V, 3V, 0V, -4V, -2V, 4V)

    DAQ/DAQe/PXI-20xx Series 4.2.3 Trigger Modes Post-Trigger Generation Use post trigger when you want to perform DA waveform right after a trigger event occurs. In this trigger mode DLY1_Counter is not used and you don’t need to specify it. Figure 4-15 shows a single waveform generated right after a trigger signal is detected.

  • Page 62: Figure 4-16: Delay Trigger Waveform Generation (Assuming The Data In The Data Buffer Are 2V, 4V, 6V, 3V, 0V, -4V, -2V, 4V)

    Figure 4-16: Delay trigger waveform generation (Assuming the data in the data buffer are 2V, 4V, 6V, 3V, 0V, -4V, -2V, 4V) Post-Trigger or Delay-Trigger with Re-trigger Use post-trigger or delay-trigger with re-trigger function when you want to generate waveform after more than one trigger events.

  • Page 63: Figure 4-18: Finite Iterative Waveform Generation With Post-Trigger And Dly2_Counter = 0 (Assuming The Data In The Data Buffer Are 2V, 4V, 2V, 0V)

    DAQ/DAQe/PXI-20xx Series Iterative Waveform Generation Set IC_Counter in order to generate iterative waveforms from the data of a single waveform. The counter stores the iteration number, and the itera-tions can be finite (Figure 4-12) or infinite (Figure 4-13). A data FIFO on board is used to buffer the digital data for DA output.
  • Page 64 Figure 4-19: Infinite iterative waveform generation with Post-trigger and DLY2_Counter = 0 (Assuming the data in the data buffer are 2V, 4V, 2V, 0V) When running infinite iterative waveform generation,  setting IC_Counter is ineffective to the waveform gen- eration. It only makes a difference when setting stop NOTE: NOTE: mode III.

  • Page 65: Figure 4-20: Stop Mode I

    DAQ/DAQe/PXI-20xx Series the waveform generation. You can apply these 3 modes to stop waveform generation no matter infinite or finite waveform gen- eration mode is selected. Figure 4-20 illustrates an example for stop mode I, in this mode the waveform stops immediately when software command is asserted.

  • Page 66: Figure 4-21: Stop Mode Ii

    Figure 4-21: Stop mode II Figure 4-22: Stop mode III Operation Theory...

  • Page 67: Digital I/O

    DAQ/DAQe/PXI-20xx Series 4.3 Digital I/O The DAQ/DAQe/PXI-20xx contains 24-lines of general-purpose digital I/O (GPIO), which is provided through a 82C55A chip. The 24-line GPIO are separated into three ports: Port A, Port B and Port C. High nibble (bit[7…4]), and low nibble (bit[3…0]) of each port can be indi-vidually programmed to be either inputs or outputs.

  • Page 68: General Purpose Timer/Counter Operation

    4.4 General Purpose Timer/Counter Operation Two independent 16-bit up/down timer/counter are designed within FPGA for various applications. They have the following fea- tures: Count up/down controlled by hardware or software  Programmable counter clock source (internal or external  clock up to 10MHz) Programmable gate selection (hardware or software control) ...

  • Page 69: General Purpose Timer/Counter Modes

    DAQ/DAQe/PXI-20xx Series 4.4.2 General Purpose Timer/Counter modes Eight programmable timer/counter modes are provided. All modes start operating following a software-start signal that is set by the software. The GPTC software reset initializes the status of the counter and re-loads the initial value to the counter. The operation remains halted until the soft-ware-start is re-executed.

  • Page 70: Figure 4-24: Mode 2 Operation

    4-24 il-lustrates the operation where initial count = 0, count-up mode. Figure 4-24: Mode 2 Operation Mode 3: Single Pulse-width Measurement In this mode the counter counts the pulse-width of the signal on GPTC_GATE in terms of GPTC_CLK. Initial count can be loaded from software.

  • Page 71: Figure 4-26: Mode 4 Operation

    DAQ/DAQe/PXI-20xx Series GPTC_GATE is used to enable/disable counting. When GPTC_GATE is inactive, the counter halts the current count value. Figure 4-26 illustrates the generation of a single pulse with a pulse delay of two and a pulse-width of four. Figure 4-26: Mode 4 Operation Mode 5: Single Triggered Pulse Generation This function generates a single pulse with programmable delay and pro-grammable pulse-width following an active...

  • Page 72: Figure 4-28: Mode 6 Operation

    Mode 6: Re-triggered Single Pulse Generation This mode is similar to mode5 except that the counter gener- ates a pulse following every active edge of GPTC_GATE. After the software-start, every active GPTC_GATE edge triggers a single pulse with programmable delay and pulse-width. Any GPTC_GATE triggers that occur when the prior pulse is not completed would be ignored.

  • Page 73: Figure 4-30: Mode 8 Operation

    DAQ/DAQe/PXI-20xx Series Mode 8: Continuous Gated Pulse Generation This mode generates periodic pulses with programmable pulse interval pulse-width following software-start. GPTC_GATE is used to enable/disable counting. When GPTC_GATE is inactive, the counter halts the current count value. Figure 4-30 illustrates the generation of two pulses with a pulse delay of four and a pulse-width of three.

  • Page 74: Trigger Sources

    4.5 Trigger Sources We provide flexible trigger selections in the DAQ/DAQe/PXI- 20xxseries products. In addition to the internal software trigger, DAQ/DAQe/PXI-20xx also supports external analog, digital trig- gers and SSI triggers. Users can configure the trigger source by software for A/D and D/A processes individually. Note that the A/D and the D/A conversion share the same analog trigger.

  • Page 75: Table 4-7: Analog Trigger Src1 (Extatrig) Ideal Transfer Characteristic

    DAQ/DAQe/PXI-20xx Series age would be 4.96V when the trigger level code is set to 0xFF while 0V when the code is set to 0x80. Figure 4-31: Analog trigger block diagram Trigger Level digital setting Trigger voltage 0xFF 9.92V 0xFE 9.84V 0x81 0.08V 0x80...

  • Page 76: Figure 4-32: Below-Low Analog Trigger Condition

    than the Low_Threshold voltage, and the High_Threshold set- ting is not used in this trigger condi-tion. Figure 4-32: Below-Low analog trigger condition Above-High analog trigger condition Figure 4-33 shows the above-high analog trigger condition, the trigger signal is generated when the input analog signal is higher than High_Threshold...

  • Page 77: Figure 4-34: Inside-Region Analog Trigger Condition

    DAQ/DAQe/PXI-20xx Series should be always higher then the Low_Threshold voltage set- ting. Figure 4-34: Inside-Region analog trigger condition High-Hysteresis analog trigger condition Figure 4-35 shows the high-hysteresis analog trigger condition, the trigger signal is generated when the input analog signal level is greater than the High_Threshold voltage, and the Low_Threshold voltage determines the hysteresis duration.

  • Page 78: Figure 4-36: Low-Hysteresis Analog Trigger Condition

    High_Threshold voltage determines the hysteresis duration. Note the High_Threshold setting should be always higher then the Low_Threshold voltage setting. Figure 4-36: Low-Hysteresis analog trigger condition External Digital Trigger An external digital trigger occurs when a rising edge or a falling edge is detected on the digital signal connected to the EXT- DTRIG or the EXTWFTRG of the 68-pin connector for external digital trigger.

  • Page 79: User-Controllable Timing Signals

    DAQ/DAQe/PXI-20xx Series 4.6 User-controllable Timing Signals In order to meet the requirements for user-specific timing and the re-quirements for synchronizing multiple cards, the DAQ/DAQe/ PXI-20xx Series provides flexible user-controllable timing signals to connect to external circuitry or additional cards. The whole DAQ timing of the DAQ/DAQe/PXI-20xx Series is com- posed of a bunch of counters and trigger signals in the FPGA.

  • Page 80: Table 4-8: Summary Of User-Controllable Timing Signals And The Corresponding Functionalities

    DAQ timing signals and the corre-sponding functionalities for DAQ/DAQe/PXI-20xx Series. Timing signal category Corresponding functionality SSI/PXI signals Multiple cards synchronization AFI signals Control DAQ-2000 by external timing signals AI_Trig_Out, AO_Trig_Out Control external circuitry or boards Table 4-8: Summary of user-controllable timing signals and the corresponding functionalities 4.6.1 DAQ timing signals...

  • Page 81: Auxiliary Function Inputs (Afi)

    DAQ/DAQe/PXI-20xx Series 4. ADCONV, the conversion signal to initiate a single con- version, which could be derived from internal counter, AFI[0] or SSI_ADCONV. Note that this signal is edge- sensitive. When using AFI[0] as the external ADCONV source, each rising edge of AFI[0] would bring an effec- tive conversion signal.

  • Page 82: Table 4-9: Auxiliary Function Input Signals And The Corresponding Functionalities

    Category Timing signal Functionality Constraints 1. TTL-compatible Replace the 2. 1MHz to 40MHz EXTTIMEBASE internal 3. Affects on both A/D TIMEBASE and D/A operations 1. TTL-compatible External digi- 2. Minimum pulse tal trigger EXTDTRIG width = 20ns Dedicated input input for A/D 3.
  • Page 83 DAQ/DAQe/PXI-20xx Series EXTTIMEBASE When the applications needs specific sampling frequency or update rate that the card could not generate from its internal TIMEBASE, the 40MHz clock, users could utilize the EXTTIME- BASE with internal counters to achieve the specific timing inter- vals for both A/D and D/A operations.

  • Page 84: System Synchronization Interface

    4.6.3 System Synchronization Interface SSI (System Synchronization Interface) provides the DAQ timing syn-chronization between multiple cards. In DAQ/DAQe/PXI-20xx Series, we de-signed a bi-directional SSI I/O to provide flexible connection between cards and allow one SSI master to output the signal and up to three slaves to receive the SSI signal. Note that the SSI signals are designed for card synchronization only, not for external devices.
  • Page 85 DAQ/DAQe/PXI-20xx Series In PXI form factor, we utilize the PXI trigger bus built on the PXI backplane to provide the necessary timing signal connections. All the SSI signals are routed to the P2 connector. No additional cable is needed. For detailed information of the PXI specifications, please refer to PXI specification Re-vision 2.0 from PXI System Alliance (www.pxisa.org).
  • Page 86 You could arbitrarily choose each of the 6 timing signals as the SSI master from any one of the cards. The SSI master can output the internal timing signals to the SSI slaves. With the SSI, users could achieve better card-to-card synchronization. Note that when power-up or reset, the DAQ timing signals are reset to use the internal generated timing signals.

  • Page 87: Calibration

    DAQ/DAQe/PXI-20xx Series Calibration This chapter introduces the calibration process to minimize AD meas-urement errors and DA output errors. 5.1 Loading Calibration Constants The DAQ/DAQe/PXI-20xx is factory calibrated before shipment by writing the associated calibration constants of TrimDACs to the Onboard EEPROM. TrimDACs are devices containing multiple DACs within a single package.

  • Page 88: Auto-Calibration

    5.2 Auto-calibration By using the auto-calibration feature of the DAQ/DAQe/PXI-20xx, the calibration software can measure and correct almost all the calibration errors without any external signal connections, refer- ence voltages, or measurement de-vices. The DAQ/DAQe/PXI-20xx has an Onboard calibration reference to ensure the accuracy of auto-calibration.

  • Page 89: Important Safety Instructions

    DAQ/DAQe/PXI-20xx Series Important Safety Instructions For user safety, please read and follow all instructions, Warnings, Cautions, and Notes marked in this manual and on the associated device before handling/operating the device, to avoid injury or damage. S'il vous plaît prêter attention stricte à tous les avertissements et mises en garde figurant sur l'appareil , pour éviter des blessures ou des dommages.
  • Page 90 Risk of explosion if battery is replaced with one of an incorrect type; please dispose of used batteries appropriately. Risque d’explosion si la pile est remplacée par une autre de CAUTION: type incorrect. Veuillez jeter les piles usagées de façon appro- priée.

  • Page 91: Getting Service

    6450 Via Del Oro, San Jose, CA 95119-1208, USA Tel: +1-408-360-0200 Toll Free: +1-800-966-5200 (USA only) Fax: +1-408-600-1189 Email: info@adlinktech.com ADLINK Technology (China) Co., Ltd. 300 Fang Chun Rd., Zhangjiang Hi-Tech Park Pudong New Area, Shanghai, 201203 China Tel: +86-21-5132-8988 Fax: +86-21-5132-3588 Email: market@adlinktech.com ADLINK Technology GmbH Hans-Thoma-Straße 11...

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