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FEATURES
§ 8051-compatible microprocessor adapts to its
task
– Accesses up to 128kB of nonvolatile
SRAM
– In-system programming through on-chip
serial port
– Can modify its own program or data
memory
– Accesses memory on a separate byte-wide
bus
– Performs CRC-16 check of NV RAM
memory
– Decodes memory and peripheral chip
enables
§ High-reliability operation
– Maintains all nonvolatile resources for
over 10 years
– Power-fail reset
– Early warning power-fail interrupt
– Watchdog timer
– Lithium backs user SRAM for
program/data storage
– Precision bandgap reference for power
monitor
§ Fully 8051-compatible
– 128kB scratchpad RAM
– Two timer/counters
– On-chip serial port
– 32 parallel I/O port pins
§ Software security available with DS5002FP
secure microprocessor
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple
revisions of any device may be simultaneously available through various sales channels. For information about device
errata, click here: http://www.maxim-ic.com/errata.
128k Soft Microprocessor Chip
PIN ASSIGNMENT (Top View)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
P0.4AD4
1
CE2
2
PE2
3
BA9
4
P0.3/AD3
5
BA8
6
P0.2/AD2
7
BA13
8
P0.1/AD1
9
R/W
10
P0.0/AD0
11
VCC0
12
VCC
13
MSEL
14
P1.0
15
BA14
16
P1.1
17
BA12
18
P1.2
19
BA7
20
P1.3
21
PE3
22
PE4
23
BA6
24
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
1 of 26
DS5001FP
64
63
62
61
60
59
58
57
56
DS5001FP
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
80-Pin MQFP
44-Pin MQFP
P2.6/A14
CE3
CE4
BD3
P2.5/A13
BD2
P2.4/A12
BD1
P2.3/A11
BD0
VLI
BA15
GND
P2.2/A10
P2.1/A9
P2.0/A8
XTAL1
XTAL2
P3.7/RD
P3.6/WR
P3.5/TI
PF
VRST
P3.4/T0
052302
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Table of Contents
Related Manuals for Maxim DS5001FP
Summary of Contents for Maxim DS5001FP
- Page 1 Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: http://www.maxim-ic.com/errata. 128k Soft Microprocessor Chip...
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Page 2: Ordering Information
The DS5001FP offers several bank switches for access to even more memory. In addition to the primary data area of 64kB, a peripheral selector creates a second 64kB data space with four accompanying chip enables. - Page 3 DS5001FP Figure 1. BLOCK DIAGRAM 3 of 26...
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Page 4: Pin Description
At this time, PSEN down externally. This should only be done once the DS5001FP is already in a reset state. The device that pulls down should be open drain since it must not interfere with under normal operation. - Page 5 This I/O pin (open drain with internal pullup) indicates that the power supply (V has fallen below the V DS5001FP drives this pin to a logic 0. Because the micro is lithium-backed, this signal is VRST guaranteed even when V low externally.
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Page 6: Instruction Set
SRAM, a lithium cell, and a real-time clock. This is packaged in a 72-pin SIMM module. MEMORY ORGANIZATION Figure 2 illustrates the memory map accessed by the DS5001FP. The entire 64k of program and 64k of data are potentially available to the byte-wide bus. This preserves the I/O ports for application use. The user controls the portion of memory that is actually mapped to the byte-wide bus by selecting the program range and data range. - Page 7 DS5001FP Figure 3. MEMORY MAP IN PARTITIONABLE MODE (PM = 0) Note: Partitionable mode is not supported when MSEL pin = 0 (128kB mode). 7 of 26...
- Page 8 DS5001FP Figure 4. MEMORY MAP WITH PES = 1 8 of 26...
- Page 9 DS5001FP Figure 5 illustrates a typical memory connection for a system using a 128kB SRAM. Note that in this configuration, both program and data are stored in a common RAM chip Figure 6 shows a similar system with using two 32kB SRAMs. The byte-wide address bus connects to the SRAM address lines. The bidirectional byte-wide data bus connects the data I/O lines of the SRAM.
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Page 10: Power Management
Low power SRAMs should be used for this reason. When using the DS5001FP, the user must select the appropriate battery to match the RAM data retention current and the desired backup lifetime. Note that the lithium cell is only loaded when V more information on this topic. -
Page 11: Absolute Maximum Ratings
11 of 26 + 0.5V) = 0V and V = 0V. In this = 0°C to +70°C; V = 5V ±10%) UNITS +0.8 + 0.3 + 0.3 0.15 0.45 0.15 0.45 µA -500 µA -600 µA DS5001FP NOTES 1, 11... - Page 12 12 of 26 = 0°C to +70°C; V = 5V ±10%) UNITS µA 4.37 4.50 4.37 4.12 4.25 4.09 4.25 µA 4.25 4.25 4.65 DS5001FP NOTES 1, 10 1, 10 3, 10 1, 2 1, 8 1, 8, 10 1, 10...
- Page 13 - 90 - 100 - 100 - 165 - 105 - 70 - 150 - 90 - 165 - 105 - 50 + 50 - 130 - 60 - 150 - 90 - 50 - 40 + 50 DS5001FP UNITS...
- Page 14 DS5001FP EXPANDED PROGRAM-MEMORY READ CYCLE EXPANDED DATA-MEMORY READ CYCLE 14 of 26...
- Page 15 DS5001FP EXPANDED DATA-MEMORY WRITE CYCLE 15 of 26...
- Page 16 External Clock-Fall Time EXTERNAL CLOCK TIMING = 0°C to +70°C; V SYMBOL at 12MHz CLKHPW at 16MHz at 12MHz CLKLPW at 16MHz at 12MHz CLKR at 16MHz at 12MHz CLKF at 16MHz 16 of 26 DS5001FP = 5V ±10%) UNITS...
- Page 17 AC CHARACTERISTICS (continued) POWER CYCLE TIME PARAMETER Slew Rate from V CCMIN Crystal Startup Time Power-On Reset Delay POWER CYCLE TIMING = 0°C to +70°C; V SYMBOL to V 17 of 26 DS5001FP = 5V ±10%) UNITS µs (Note 9) 21,504...
- Page 18 Clock-Rising Edge to Input-Data Valid Input-Data Hold After Rising-Clock Edge SERIAL PORT TIMING, MODE 0 = 0°C to +70°C; V SYMBOL SPCLK - 133 DOCH - 117 CHDO CHDV CHDIV 18 of 26 DS5001FP = 5V ±10%) UNITS µs - 133...
- Page 19 RWLDV 1-4, CEHDV High RWHDV Low Time) RWLPW 19 of 26 = 0°C to +70°C; V = 5V ±10%) - 35 CEPW - 20 + 40 - 30 - 35 + 40 - 35 - 15 - 20 DS5001FP UNITS...
- Page 20 BYTE-WIDE BUS TIMING RPC AC CHARACTERISTICS, DBB READ (T PARAMETER Setup to Hold After Pulse Width to Data-Out Delay to Data-Out Delay to Data-Float Delay = 0°C to +70°C; V SYMBOL 20 of 26 DS5001FP = 5V ±10%) UNITS...
- Page 21 High to Inactive PROG = 0°C to +70°C; V SYMBOL = 0°C to +70°C; V SYMBOL = 0°C to +70°C; V PROG SYMBOL 21 of 26 DS5001FP = 5V ±10%) UNITS = 5V ±10%) UNITS = 5V ±10%) UNITS CLKS CLKS...
- Page 22 DS5001FP RPC TIMING MODE 22 of 26...
- Page 23 = 0V and V < V , and a maximum load of 10µA on V ³ 3.0V. 23 of 26 , MSEL = V , RST = MSEL = V ; XTAL2 not = +25°C. in normal operation. is disconnected. DS5001FP CLKR CLKR...
- Page 24 80-PIN MQFP 3.40 0.25 2.55 2.87 0.30 0.50 0.13 0.23 23.70 24.10 19.90 20.10 17.70 18.10 13.90 14.10 0.80 BSC 0.65 0.95 56-G4005-001 24 of 26 DS5001FP...
- Page 25 DS5001FP 44-PIN MQFP 25 of 26...
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Page 26: Revision History
REVISION HISTORY The following represent the key differences between 112795 and 073096 version of the DS5001FP data sheet. Please review this summary carefully. 1) Change V specification from V CC02 2) Update mechanical specifications. The following represent the key differences between 073096 and 111996 version of the DS5001FP data sheet.