Kenwood TK-2160 Service Manual page 8

TK-2160
6) Tone Volume Fixed Circuit
This function generates a TONE signal sound even if the
AF volume of the transceiver is the minimum.
A TONE signal is sent through Q602 to the AF amplifier
w hen, in the FPU, " TONE Volume Fixed" is set to ON.
BEEP
IC805
CPU
TONE VOL FIXED
BEEPSW
+
[VOL Position vs Output Level]
500
ON
25
M in
Fig. 4 Tone volume fixed circuit
7) Squelch
Part of the AF signal from the IC enters the FM IC (IC401)
again, and the noise component is amplified and rectified
by a f ilt er and an am plif ier t o produce a DC volt age
corresponding to the noise level.
The DC signal from the FM IC goes to the analog port of
the microprocessor (IC805). IC805 determines w hether
to output sounds from the speaker by checking w hether
the input voltage is higher or low er than the preset value.
To output sounds from the speaker, IC805 sends a high
signal to the SP M UTE line and turns IC605 on through
Q603,Q604,Q607 and Q608. (See Fig. 5)
8) Receive Signalling
(1) QT/DQT
Th e o u t p u t s ig n al f ro m IF IC(IC4 0 1 ) e n t e rs t h e
microprocessor(IC805) through IC601. IC805 determines
w hether the QT or DQT matches the preset value, and
controls the SP M UTE and the speaker output sounds
according to the squelch results.
(2) 2-TONE
Part of the received AF signal output from the AF amplifier
IC602, and t hen passes t hrough an audio processor
(IC601), goes to the other AF amplifier IC603, is compared,
and then goes to IC805. IC805 checks w hether 2-TONE
dat a is necessary. If it m at ches, IC805 carries out a
specified operation, such as turning the speaker on. (See
Fig. 5)
8
CIRCUIT DESCRIPTION
IC601
VOL
AQUA
IC605
TA7368F
Q602
Hi: ON
LOW: OFF
SP-J
SP
OFF
Center M ax
(3) M SK (Fleet Sync)
Fleet Sync utilizes 1200bps and 2400bps M SK signal is
output from pin 6 of IC601. And is routed to the VCO.
When encoding M SK, the microphone input signal is muted.
RECEIVE SIGNALING RECEIVE SIGNALING
FM IF IC401
IC602
IF Am p IF Am p
SIGNAL
DTM F
QT/DQT
IC805
CLK,DATA,
LSDI
AN SQL
STD,LOADN
IC603
CPU BPF & COMPALATER
HSDI
2-TONE
SP M UTE
Fig. 5 AF amplifier and squelch
(4) DTM F
The DTM F input signal from the IF IC (IC401) is amplified
by IC602 and goes to IC601. The decoded information is
then processed by the CPU.
3. PLL Frequency Synthesizer
The PLL circuit generates the first local oscillator signal for
reception and the RF signal for transmission.
1) PLL
The frequency step of the PLL circuit is K:2.5,5,6.25 or
7.5kHz, M :6 or 6.25kHz.
A 16.8M Hz reference oscillator signal is divided at IC1 by a
fixed counter to produce an oscillator (VCO) output signal
w hich is buffer amplified by Q9 then divided in IC1 by a
dual-module programmable counter. The divided signal is
compared in phase w ith the 5 or 6.25kHz reference signal
from the phase comparator in IC1. The output signal from
the phase comparator is filtered through a low -pass filter
and passed to the VCO to control the oscillator frequency.
(See Fig. 6)
2) VCO
The operating frequency is generated by Q6 in transmit
mode and Q5 in receive mode. The oscillator frequency is
controlled by applying the VCO control voltage, obtained
f rom t he phase com parat or, t o t he varact or diodes
(D3,D5,D7 and D8 in transmit mode and D4,D6,D9 and D10
in receive mode). The RX pin is set high in receive mode
causing Q8 and Q12 to turn Q6 off and Q5 on.
The TX pin is set high in transmit mode. The outputs from
Q5 and Q6 are amplified by Q9 and sent to the RF amplifiers.
IC601
AQUA
SP
IC605 Q608
AF PA SW
Q603,604,607
SW