Sharp LC-32LE700E Service Manual page 91

2.18. IC1504 (VHiSiI9287+-1Q)
2.18.1 Block Diagram
SiI9287
HDMI PORT PROCESSOR
50 CEC_A
31 HPD0
35 HPD1
29 DSDA0,
30 DSCL0
33, DSDA1,
34 DSCL1
DDC0
39, DSDA2,
DDC1
40 DSCL2
DDC2
43, DSDA3, DDC3
44 DSCL3 DDC4
48, DSDA4,
47 DSCL4
54 CSCL
53 CSDA
LOCAL
I2C
32 R0PWR5V
36 R1PWR5V
42 R2PWR5V
46 R3PWR5V
49 R4PWR5V
68,67
R0X0P/N
70,69
R0X1P/N
72,71
R0X2P/N
66,65
R0XCP/N
PORT0
4,3
R1X0P/N
6,5
R1X1P/N
8,7
R1X2P/N
2,1 R1XCP/N
PORT1
14,13
R2X0P/N
16,15
R2X1P/N
18,17
R2X2P/N
R2XCP/N
12,11
PORT2
22,21,
R3X0P/N
24,23,
R3X1P/N
26,25
R3X2P/N
R3XCP/N
20,13
PORT3
2.18.2 Pin Connections and short description
Pin No. Pin Name
HDMI RX Port Pins
68 R0X0P
67 R0X0N
70 R0X1P
69 R0X1N
72 R0X2P
71 R0X2N
66 R0XCP
65 R0XCN
4 R1X0P
3 R1X0N
6 R1X1P
5 R1X1N
8 R1X2P
7 R1X2N
2 R1XCP
1 R1XCN
14 R2X0P
13 R2X0N
16 R2X1P
15 R2X1N
LC-32/40/46LE700E/RU/S,LU700E/S,LX700E/RU,LC-52LE700E/RU/S
MHL Control
EDID SRAM
HDCP REG
TMDS
DPLL/DEC
SCDT
MHL
DP
I/O
I TMDS input port 0 data pairs.
I
I
I
I
I
I TMDS input port 0 clock pair.
I
I TMDS input port 1 data pairs.
I
I
I
I
I
I TMDS input port 1 clock pair
I
I TMDS input port 2 data pairs.
I
I
I
CPI REG
NV RAM
OTP
HDCP ENGINE
HDMI DATAPATH
Pin Function
7 – 25
ALWAYS_ON
CEC_D 51
CEC
Controller
41
HPD2
45
HPD3
BOOTING
SEQUENCER
INT 52
CONFIG
STATUS REG
VCC33
9,27,64
MICOM_VCC33
37
SBVCC
38
POWER_DOWN
60,61
TX0P/N
58,59
TX1P/N
56,57
TX2P/N
TXCP/N 62,63