Ic Block Diagram - Aiwa XR-M88 Service Manual

Pin No. Pin Name I/O
43 XVDD — Crystal oscillator power supply pin.
44 XOUT O
Pin to which external 16.9344 MHz crystal oscillator is connected.
45 XIN I
46 XVSS — Crystal oscillator GND pin. Be sure to connect to 0V.
47 SBSY O Subcode block sync signal output pin.
48 EFLG O C1, C2, single and dual correction monitoring pin.
49 PW O Subcode P, Q, R, S, T, U and W output pin.
50 SFSY O Subcode frame sync signal output pin. Falls down when subcode enters standby.
Subcode read clock input pin. Schmidt input. (Be sure to connected to 0V when not
51 SBCK I
in use.)
Pin outputting the 7.35 kHz sync signal which is generated by dividing frequency of
52 FSX O
crystal oscillator.
53 WRQ O Subcode Q output standby output pin.
54 RWC I Read/write control input pin. Schmidt input.
55 SQOUT O Subcode Q output pin.
56 COIN I Command input pin from microprocessor.
___________
57 CQCK I Command input read clock or subcode read input clock from SQOUT pin
________
58 RES I LC78622 reset input pin. Set this pin to L once when the main power is turned on.
59 TST11 O Test signal output pin. Use this pin as open (normally L output).
60 16M O 16.9344 MHz output pin.
61 4.2M O 4.2336 MHz output pin.
62 TEST5 I Test signal input pin with built-in pull-down resistor. Be sure to connect to 0V.
Chip select signal input pin with built-in pull-down resistor. Be sure to connect to 0V
______
63 CS I
while it is not controlling.
64 TEST1 I Test signal input pin without built-in pull-down resistor. Be sure to connect to 0V.
Note: The same potential must be applied to the respective power supply terminals. (VDD, VVDD, LVDD, RVDD, XVDD)
Description
61

IC BLOCK DIAGRAM

IC, BA5936
IC, M62495FP
IC, BA3880FS
IC, MM1454XFBE
VCC LIN VREF
16 15
+
–
1 2
RIN PNR
Rog CURRENT
DETECTOR
TERMINAL
QF1 QF2 QF3 QF4 QF5
14 13 12 11 10 9
QSurround
BIAS
+
–
3 4 5 6 7 8
B/Q DET QF6 ROUT LOUT GND
62