Yamaha DVX-700 Service Manual page 74

DVR-700/NS-PSW700/NS-P700
Pin No. Function Name
61 RX2
62 NC
63 RX3
64 PVSS
65 R
66 PVDD
67 RX4
68 TEST2
69 RX5
70 CAD0
71 RX6
72 CAD1
73 RX7
74 I2C
75 DAUX2
76 VIN
77 MCLK
78 TX0
79 TX1
80 INT0
Note: All input pins except internal biased pins and internal pull-down pin should not be left floating.
74
I/O
I Receiver channel 2 pin (Internal biased pin / Internally biased at PVDD/2)
No connect pin
–
No internal bonding / This pin should be connected to PVSS
I Receiver channel 3 pin (Internal biased pin / Internally biased at PVDD/2)
– PLL ground pin
External resistor pin
–
12 k-ohms +/-1 % resistor should be connected to PVSS externally
– PLL power supply pin, 4.5 V to 4.5 V
I Receiver channel 4 pin (Internal biased pin / Internally biased at PVDD/2)
Test 2 pin
I
This pin should be connected to PVSS
I Receiver channel 5 pin (Internal biased pin / Internally biased at PVDD/2)
I Chip address 0 pin (ADC/DAC part)
I Receiver channel 6 pin (Internal biased pin / Internally biased at PVDD/2)
I Chip address 1 pin (ADC/DAC part)
I Receiver channel 7 pin (Internal biased pin / Internally biased at PVDD/2)
Control mode select pin
I
"L": 4-wire serial, "H": I2C bus
I Auxiliary audio data input pin (DIR/DIT part)
I V-bit input pin for transmitter output
I Master clock input pin
O Transmit channel (through data) output 0 pin
Transmit channel output 1 pin
O When TX bit = "0", transmit channel (through data) output 1 pin.
When TX bit = "1", transmit channel (DAUX2 data) output pin (default)
O Interrupt 0 pin
Detail of Function