Yamaha DVX-700 Service Manual page 104

A B C
DVR-700/NS-PSW700/NS-P700
MAIN 4/4
1
2
L/R
3
SW
4
5
6
7
8
9
10
104
D E F
12.0
4.3
0
0
4.3
1.7
3.3
0
0
0
3.3
0
3.3
0
0
1.8
1.7
3.3
3.4 1.7
0
0
1.7
0
0
0
0.9
12.0
0.9 12.0
0 3.3
1.8
1.9
5.0
0
5.0
3.4 0
3.3
0
0 1.3
0.7
1.1
1.9 0
5.0 0
5.1
12.0
5.1 0
1.7
1.7
4.3
0
0
4.3
1.7
3.3
0
0
0
0
3.3
0
3.3
0
1.7
3.3
0
0
0
12.0
12.0
Page 105 K7
to SUB_W206
IC800: TAS5086DBT
PWM processor
DVDD
DVSS
DVSS_ESD
VR_DIG
Power
VR_ANA
Supply
VR_OSC
AVDD
AVSS_PLL
VREG_EN
Chan.
SDIN1 1-6
Serial
SDIN2
Data MUX
SDIN3
Interface
SDIN4
SDIN4 1-5 1-5 L'
Channel
Down-
Selector
mix R'
Block
MCLK
SCLK
LRCLK Clock Rate
PLLFLTP /Error
PLLFLTM Detection
(L'+R')/2
HFCLK and PLL
OSCFLT
OSC_RES
1-6
SDA Serial
Control
SCL
Interface
RESET
PDN System
MUTE Control
BKNDERR
G H I
12.0
26.3
0
OUT L
30.3
30.3
15.1
0
0
15.1
30.3
26.3
11.6
30.3
15.1
0
0
10.3
30.3
30.3
0
11.4
12.0
12.0
26.3
0
30.3
30.3
15.1
0
0
15.1
30.3
26.3
11.6
OUT SW
30.3
15.1
0
0
15.1
30.3
30.3
0
11.4
12.0
1LF
6
MUX MUX PWM1
L'
2RF
6
MUX
R' MUX PWM2
6
3LS
MUX PWM3
VR_ANA 1 38 PWM_1
Ch
1-6 AVDD 2 37 PWM_2
Vol PWM 6 AVSS 3 36 PWM_3
4RS
MUX PWM4 AVSS 4 35 PWM_4
PLL_FLTM 5 34 PWM_5
5C
6 PLL_FLTP 6 33 PWM_6
(L'+R')/2 MUX MUX PWM5 AVSS 7 32 VALID2
MCLK 8 31 VALID1
RESET 9 30 VR_DIG
6
MUX PWM6
PDN 10 29 DVSS
Channel Six Processing
Bass Management DVDD 11 28 DVSS
DVSS 12 27 BKND_ERR
DVSS_OSC 13 26 SDIN1
OSC_RES 14 25 SDIN2
PWM VALID1
Control VR_OSC 15 24 SDIN3
VALID2
MUTE 16 23 SDIN4
Downmix
I2S Serial SDA 17 22 SDOUT
SDIN4 MUX SDOUT
Output
SCL 18 21 RESERVED
LRCLK 19 20 SCLK
J K
DRIVER
WOOFER
CB802
IC801, 802: TAS5342LDDV
100 W stereo digital amplifier power stage
21 VDD
4
Under-
OTW 2 voltage 4
Protection
Internal Pullup VREG 12 VREG
Resistors to VREG
SD 5
Power
On
M1 15 Reset
11 AGND
Protection
and
M2 14
I/O Logic
Temp.
M3 13
Sense 10 GND
RESET_AB 7
Overload
Isense 9 OC_ADJ
RESET_CD 17 Protection
23 GVDD_D
24 BST_D
26, 27 PVDD_D
PWM Gate
Ctrl. Timing 28 OUT_D
PWM_D 18 Rcv. Drive
BTL/PBTL-Configuration
Pulldown Resistor
29 GND_D
22 GVDD_C
33 BST_C
32 PVDD_C
PWM Gate
PWM_C 16 31 OUT_C
Ctrl. Timing Drive
Rcv.
BTL/PBTL-Configuration
Pulldown Resistor
30 GND_C
1 GVDD_B
34 BST_B
35 PVDD_B
PWM Gate
36 OUT_B
PWM_B 8 Ctrl. Timing Drive
Rcv.
BTL/PBTL-Configuration
Pulldown Resistor
37 GND_B
44 GVDD_A
43 BST_A
40, 41 PVDD_A
PWM Gate
PWM_A 6 Ctrl. Timing 39 OUT_A
Rcv. Drive
BTL/PBTL-Configuration
Pulldown Resistor
38 GND_A
L M N