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HEAD_INT
N3
KBR0, KBR1, KBR2
H2, H3, H1
DSC_RXD
DSC_TXD
( Keyboard )
KBC0, KBC1, KBC2, KBC3
K1, J4, J3, J2
HS_INT
K2
DP_EN
E10
P4
K4
VIB_EN
LED_RED
M3
LED_GRN
M2
LS1_IN
E8
LS2_IN
D6
LS3_TX
E1
LS3_RX
E6
CLK_SELCT
C3
A1
TX_EN
D2
C1
DM_CS
F5
E2
TX_KEY
E1
E4
E2
RX_EN
E3
RX_ACQ
E3
E4
M4
P2
RESET
PB2
L2
( SDTX ) BDX
C6
( TX_CLK ) BCLKX
A2
( SCLK_OUT ) BCLKR
from / to MAGIC
A3
BKLT_EN
( SDFS ) BFSR
B4
J 600
( SDRX ) BDR
V2
C4
Q911
13
K2
DSC_EN
Q912
V1
DSC_EN_AD
6
PC_RXD
From PDA
Q803
( for RS232 )
7
PC_TXD
To PDA
4
BATT FDBK
UTXD URXD
To / From PDA
EXT_B+
14
EXT_B+
2
SW_RF
ON / OFF
(From Switch)
8
9
On/Off
1
CR920
GND
3
GND
10
GND
GND
15
( Ext Accessory Sense)
5
MAN_TEST_AD
DSC_EN_AD
DOWNLINK_AD
VS944
BATT_THERM
ISENSE
LS_V1
GCAP UPLINK
GCAP_DOWNLINK
LS_V1
RESET
DSC_TXD
11
From PDA
UPLINK
DSC_RXD
12
DOWNLINK
To PDA
SR_VCC
DOWNLINK_AD
MIC
J910
HEAD_INT
HEADSET
J504
U980
BOOM_PWR
G1
F4
A4
C14, D4, E12, H4, J10, K6, N12
B5, B9, B10, G12, K14, L11, N8
( CE ) MQSPI_CS1
U700
L8
WHITE_CAP
( SPI_CLK ) MOSPI_CLK1
KEYPAD
SPI
M8
( SPI_DATA ) DX1
INTERFACE
DISPLAY
M7
INTERFACE
M
E
M
SIM
O
INTER
R
Y
FACE
( Flip Con. )
I
CPU
N
T
C9
CTM
E
E9
MODULE
R
D11
F
A
D9
C
E
A9
Baseband
to Digital
SERIAL
Speech
CTM
F3
DSP
INTER
-5V_EN
N6
FACE
A / D
CHARGE
DSC
UART
SPI
INTERF.
TIMER
INTERFACE
D7
K5 G14
D5
A6
SR_CS
F5
C7
A7
B7
D6
SELECT
SPI
G5
REAL TIME
INTERFACE
SENSE
CLOCK
CNTL
U900
A1
LEVEL
B2
SENSE
SHIFT
A2
G_CAP2
B3
CNTL.
D9
D2
C3
C4
Logic Control
VREF
C2
REG.
V3
C1
REG.
V2
E1
REG.
J2
V1
REG.
VSIM
Interface
REG.
Audio
H3
Codec
VBOOST1
H2
REG.
H6 H7
H9
K5
B10
Q902
LX
Q9808
SPKR
J9833
ALRT_VCC
Q938
TO PDA
L901
B+
B+
V2
V3
PRESENCE DETECT
( MAGIC SPI )
DATA BUS
ADDRESS BUS
R_W
V2
D6, E1
CE2
B2
U702
CE3
A1
SRAM
R_W
SR_VCC
G6
E1 & D6
LS_V1
2
1
5
U901
-5V
EXT B+
Q901
B+
Q9819
RTC BATT
J9844
CR940
Q932
CR932
R932
I SENSE
D9
E8
CHRGC
BATT+
F7
B+
E10
CLK
F6
6
J900
RST
SIM
J7
4
Con.
SIM_I/O
J8
5
2
1
VSIM1
K7
LS2_IN
G6
LS1_IN
(SIM_TX)
K10
LS3_TX
H8
LS3_RX
(SIM_RX)
C8
PWR_SW
G4
STDBY
G9
VREF
2.775V,for MAGIC
B5
V3
1,8V, for WhiteCap
J5
V2
2.775V, for WhiteCap logic outputs, RAM, FLASH, EEPROM
A6
LS_V1
5.0V, for DSC Bus, Negative Voltage Regulator
C6
VSIM1
3.0 or 5.0V, for SIM Card Circuit
A10, C10
CR901
V_BOOST1
Internal GCap use only (VSIM1, LS_V1)
V2
V2
BATT_+
STBY
Q628
U950
R627
BATT_THERM
V2
A4, A6, F6
RESET
U701
B4
EPROM
EEPROM
CE0
D7
CE1
F8
DEEP SLEEP
STDBY
V1
CIRCUIT
LS_V1
V2 & VREF Grounded
BATT +
CHRG_EN
BATT +
Q634
Q942
BATT FDBK
Q920
V1
GLOBAL GSM SERVICE SUPPORT
LEVEL 3 AL Block Diagram
TAI CHI PLUS ORGANISER
Ralf Lorenzen, Michael Hansen, Ray Collins
BKLT+
( Flip Con. )
Q938
BATT CONNECTOR
J611
J614
J610
THERM
BATT +
N/C
J613
J612
BATT_SER_DATA
GND
J810
( WhiteCap )
VIB_EN
1
U801
4
5
B+
J811
KBC0
HOME
KBR0
PAGE UP
KBR1
PAGE DOWN
PWR_SW
POWER ON / OFF
KBR0
VA
CCW
CW
Jog Switch
KBC1
KBR2
( GCAP2 )
V2
3
5
LED_RED
Q805
6
( WhiteCap )
2
4
LED_GRN
Q805
1
RX SIGNAL PATH
TX SIGNAL PATH
MAIN VCO SIGNAL PATH
TUNING VOLTAGES
REFERENCE CLOCK
Orderable Part
Non - Orderable Part
15.01.01
Rev. 1.1
Page 2
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