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R5F3650TNFB Block Diagram
Port P0
Internal peripheral functions
Remote control signal receiver
Port P10
Notes :
1. ROM size depends on MCU type.
2. RAM size depends on MCU type.
R5F3650TNFB Terminal Function
Pin
PIN
PIN NAME
No.
1 P94
VPLD DATA
2 P93
DIR CE
3 P92/SOUT3
DIR DIN
4 P91/SIN3
DIR DOUT
5 P90/CLK3
DIR CLK
6 BYTE
BYTE
7 CNVCS
CNVSS
8 P87
NC
9 P86
OSD CPU BUSY
SO
10 RESET
SUBRESET
11 XOUT
X1
12 VSS
VSS
13 XIN
X2
14 VCC
VCC
15 P85/NMI/
NMI/(CEC_IN)
(CEC)
16 P84/INT2
CEC_IN
17 P83/INT1
ACK SIMO
18 P82/INT0
SUB BDOWN
19 P81
IP RST
20 P80/(RXD5)
TDO
8
8
Port P2
VCC1 ports
clock synchronous serial I/O
Timer (16-bit)
Outputs (timer A) : 5
Inputs (timer B) : 6
Clock synchronous serial I/O
Multi-master I
Real time clock
PWM function (8 bits X 2)
(2 circuits)
Watchdog timer
(15 bits
X 1)
A/D converter
M16C/60 series CPU core
(10 bits X 26 channels)
D/A converter
(8 bits X 2 channels)
VCC1 ports
Port P9
Port P8
8
7
8
Op
I/O Type
Det
(in)
O
C
-
-
O
C
-
-
O
C
-
-
I
-
Lv
-
O
C
-
-
-
-
-
-
-
-
-
-
O
C
-
-
O
C
-
-
I
-
Lv
-
O
-
-
-
-
-
-
-
I
-
-
-
-
-
-
I
-
-
-
I
-
-
E↓& L
I
-
-
E↓& L
I
-
E↓& L
O
C
-
-
I
-
-
-
AVR-2310CI/2310/890, AVC-2310
8
4
Port P3
Port P4
Port P5
System clock generator
UART or
(3 channels)
PLL frequency synthesizer
UART
On-chip oscillator (125 kHz)
(1 channel)
High-speed on-chip oscillator
(8 bits x 2 channels)
2
C bus interface
(1 channel)
CRC arithmetic circuit
CEC function
Voltage detection circuit
R0H
R0L
SB
R1H
R1L
USP
R2
ISP
R3
INTB
A0
PC
A1
FB
FLG
Port P7
Port P6
4
8
PURE
Op(ex) Res
CEC STBY
D
-
Z
O/L
O/L
-
Z
O/L
O/L
-
Z
O/L
O/L
Eu
Z
-
-
-
Z
O/L
O/L
-
-
-
-
Ed47k
-
-
-
Eu
Z
O/H
O/H
-
Z
O/L
O/L
Eu
L
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Eu
Z
-
-
Ed
Z
-
-
Eu
Z
-
-
-
Z
O/H
O/H
-
Z
Z
-
48
8
XIN-XOUT
XCIN-XCOUT
DMAC
(4 channels)
(CCITT or CRC-16)
Power-on reset
On-chip debugger
Memory
(1)
ROM
(2)
RAM
Multiplier
P.OF
Function
F
Z
FPGA control
Z
DIR(LC89058W-VF4A) control
Z
DIR(LC89058W-VF4A) control
Z
DIR(LC89058W-VF4A) control
Z
DIR(LC89058W-VF4A) control
-
GND
-
Firmware update control
Z
Z
Interface between Sub CPU and D.OSD CPU
Z
RESET pulse input
-
Oscillator connect
-
GND
-
Oscillator connect
-
+3.3V
-
Connect to +3.3V
Z
CEC control
Z
Interface between Main CPU and Sub CPU
Z
Power off detect
Z
IP CONV.(ABT2010) control
Z
FPGA firmware update control (JTAG)
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