M30879Flbfp Block Diagram; M30879Flbfp Terminal Function - Denon AVR-2310 Service Manual

M30879FLBFP Block Diagram

Port P0
Internal peripheral functions
Timers (16 bits)
Output (timer A): 5
Input (timer B): 6
Three-phase motor
control circuit
Watchdog timer (15 bits)
Serial interface: 7 channels
Time measurement function:
8 channels
Waveform generation
function: 16 channels
Communication function:
clock synchronous serial
interface, UART, HDLC
data processing, IEBus
CAN modules:2 channels
Port P13
8
NOTES:
1. Ports P11 to P15 are provided in the 144-pin package only.
2. 34 channels are available in the 144-pin package. 26 channels are available in the 100-pin package.
3. 6 channels are available in the 100-pin package.
4. 10 channels are available in the 100-pin package.
5. M32C/87A has 1 channel. M32C/87B has no CAN module.
Figure 1.2 M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Block Diagram
M30879FLBFP Terminal Functio
PIN
PIN PIN NAME
No.
1 P96/TXD4 NC
2 P95/(CLK4) MICDET
3 P94 H/PDET
4 P93 FL_DATA
5 P92/TXD3 MOSI
6 P91/RXD3 SOMIm
7 P90/CLK3 CLKMO
8 BYTE BYTE
9 CNVCS CNVSS
10 P87 FL_RST
11 P86 GRNLED
12 RESET RESET
13 XOUT XOUT
14 VSS VSS
15 XIN XIN
16 VCC VCC
8 8 8
Port P1 Port P2 Port P3
<VCC2>
10-bit A/D converter:
1 circuit
34 channels for input
8-bit D/A converters:
2 circuits
X/Y converter:
16 bits X 16 bits
(3)
DMAC: 4 channels
Intelligent I/O
M32C/80 Series CPU core
(4)
(5)
<VCC2>
(1) (1) (1)
Port P12 Port P11 Port P15
8 5
n
Lv Op
I/O Type DET
Cnv (in)
O C - - -
I - Lv - -
I - Lv - -
O C - -
O C - 5/3 -
I - Lv 5/3 -
O C - 5/3 -
I - - - -
I - - - -
O C - -
O C - - -
I - Lv - -
O - - - -
- - - -
I - - - -
- - - - -
AVR-2310CI/2310/890, AVC-2310
8 8 8
Port P4 Port P5
Clock generation circuits:
XIN-XOUT
(2) XCIN-XCOUT
On-chip oscillator
PLL frequency synthesizer
CRC calculation circuit
(CCITT):
16
X + X
R1H R1L
R0H R0L FLG
R1H R1L
R1H R1L INTB
R2 ISP
R3 USP
A0 PC
A1 SVF
FB SVP
SB VCT
<VCC1>
(1) (1)
Port P14 Port P10 Port P9
8 7 8
Op PURE CEC STBY
Res
(ex) D STBY STOP
- Z - O/L O/L
Eu Z - - O/L
Eu Z - - O/L
- Z - O/L O/L
- Z - - O/L
- Z - - I
- Z - - O/L
- - - - -
Ed Z - - I
- Z - O/L O/L
- Z - O/L O/L
Eu L - - I
- - - - -
- - - - -
- - - - -
- - - - -
44
8 8
Port P6 Port P7
<VCC1>
12 5
+ X + 1
DMACII
Memory
ROM
RAM
Multiplier
P8_5 Port P8
8 7
P.OFF
STOP
O/L UART
O/L Mic insert detect
O/L Headphone insert detect
O/L FL display unit control
O/L Interface between Main CPU and
Sub CPU
O/L Interface between Main CPU and
Sub CPU
O/L Interface between Main CPU and
Sub CPU
- GND
I Firmware update control
O/L FL display unit control
O/L H : ON Power indicator (green led) control
I Reset signal input
- Oscillator connect
- GND
- Oscillator connect
- POWER 5V
Function