Ic Description - Aiwa CSD-MD50 Service Manual

IC DESCRIPTION

IC, CXD2652AR
Pin No. Pin Name
1 MNT0
2 MNT1
3 MNT2
4 MNT3
5 SWDT
6 SCLK
7 XLAT
8 SRDT
9 SENS
10 XRST
11 SQSY
12 DQSY
13 RECP
14 XINT
15 TX
16 OSCI
17 OSCO
18 XTSL
19 NC
20 DVSS
21 DIN
22 DOUT
23 ADDT
24 DADT
25 LRCK
26 XBCK
27 FS256
28 DVDD
29 A03
30 A02
31 A01
32 A00
33 A10
34 A04
35 A05
36 A06
37 A07
38 A08
39 A11
I/O
O Monitor output pin.
O Monitor output pin.
O Monitor output pin.
O Monitor output pin.
I Data input pin for micro-processor serial interface.
I Shift clock input pin for micro-processor serial interface.
I Latch input pin for micro-processor serial interface. Shut down: Latch.
O Data output pin for micro-processor serial interface.
O Output internal status according to micro-processor serial interface address.
I Reset input pin. "L": Reset.
O Disc sub-code Q synchronize / ADIP synchronize output.
When source of the digital in is set to CD or MD, output sub-code Q synchronize of
O
UbitCD or MD format.
I Laser power switching input pin. "H": Record power. 'L": Playback power.
O Intrusion demand output pin. "L" setting when intrusion demand status is generated.
I Record data output enable signal input pin. "H": Enable.
I Crystal oscillator circuit input pin.
O Crystal oscillator circuit output pin. (OSCI inverted output)
Switch input frequency of OSCI pin. (Connected to DVDD)
I
"H": 512Fs (22.5792MHz), "L": 1024Fs (45.158MHz).
– Not used. (Connected to DVDD)
– Digital GND.
I Input digital audio interface signal.
O Output digital audio interface signal.
I Analog record input pin. (Connected to external A/D converter output)
O REC monitor output pin / Output decode audio data.
O Output LRCK (44.1kHz) to external audio block.
O Output bit clock (2.8224MHz) to external audio block.
O Output 256Fs (11.2896MHz).
– Digital power supply.
O Output address for external DRAM.
O Output address for external DRAM.
O Output address for external DRAM.
O Output address for external DRAM.
O Output address for external DRAM. (Not used)
O Output address for external DRAM.
O Output address for external DRAM.
O Output address for external DRAM.
O Output address for external DRAM.
O Output address for external DRAM.
O Output address for external DRAM. (Not used.)
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Description