Sony D-V7000 Service Manual page 23

Pin No. Pin Name
46 DATA
47 BCLK
48 64 DATA
49 64 BCLK
50 64 LRCK
51 GTOP
52 XUGF
53 XPLCK
54 GFS
55 RFCK
56 C2PO
57 XRAOF
58 MNT3
59 MNT2
60 MNT1
61 MNT0
62 XTAI
63 XTAO
64 XTSL
65 DVSS
66 FSTI
67 FSTO
68 C4M
69 C16M
70 MD2
71 DOUT
72 EMPH
73 WFCK
74 SCOR
75 SBSO
76 EXCK
77 SUBQ
78 SQCK
I/O
DA16 output when PSSL="H", 48-bit slot serial data output when PSSL="L"
(PSSL (pin $£)=fixed at "L") Serial data output to the D/A converter (IC320) and MPEG
O
audio/video decoder (IC901)
DA15 output when PSSL="H", 48-bit slot bit clock signal output when PSSL="L"
(PSSL (pin $£)=fixed at "L") Bit clock signal (2.8224 MHz) output to the D/A converter
O
(IC320) and MPEG audio/video decoder (IC901)
DA14 output when PSSL="H", 64-bit slot serial data output when PSSL="L"
O
(PSSL (pin $£)=fixed at "L")
DA13 output when PSSL="H", 64-bit slot bit clock signal output when PSSL="L"
O
(PSSL (pin $£)=fixed at "L")
DA12 output when PSSL="H", 64-bit slot L/R sampling clock signal output when PSSL="L"
O
(PSSL (pin $£)=fixed at "L")
DA11 output when PSSL="H", GTOP signal output when PSSL="L"
O
(PSSL (pin $£)=fixed at "L")
DA10 output when PSSL="H", XUGF signal output when PSSL="L"
O
(PSSL (pin $£)=fixed at "L")
DA09 output when PSSL="H", XPLCK signal output when PSSL="L"
O
(PSSL (pin $£)=fixed at "L")
DA08 output when PSSL="H", GFS (guard frame sync) signal output when PSSL="L"
O
(PSSL (pin $£)=fixed at "L")
DA07 output when PSSL="H", RFCK (read frame clock) signal output when PSSL="L"
O
(PSSL (pin $£)=fixed at "L")
DA06 output when PSSL="H", C2PO signal output when PSSL="L"
O
(PSSL (pin $£)=fixed at "L")
DA05 output when PSSL="H", XRAOF (RAM over flow) signal output when PSSL="L"
O
(PSSL (pin $£)=fixed at "L")
DA04 output when PSSL="H", MNT3 (monitor 3) signal output when PSSL="L"
O
(PSSL (pin $£)=fixed at "L")
DA03 output when PSSL="H", MNT2 (monitor 2) signal output when PSSL="L"
O
(PSSL (pin $£)=fixed at "L")
DA02 output when PSSL="H", MNT1 (monitor 1) signal output when PSSL="L"
O
(PSSL (pin $£)=fixed at "L")
DA01 output when PSSL="H", MNT0 (monitor 0) signal output when PSSL="L"
O
(PSSL (pin $£)=fixed at "L")
I Master clock signal (16.9344 MHz) input from the D/A converter (IC320)
O Master clock output terminal (16.9344 MHz) Not used (open)
I Master clock selection input terminal (fixed at "L")
— Ground terminal (digital system)
2/3 divider input terminal of pins ^™ (XATI) and ^£ (XTAO)
I
2/3 divider output terminal of pins ^™ (XATI) and ^£ (XTAO)
O
O 4.2336 MHz clock signal output terminal Not used (open)
O 16.9344 MHz clock signal output terminal Not used (open)
I Digital out on/off control signal input terminal Fixed at "H" in this set
O Digital signal (for coaxial out and optical out) output terminal Not used (open)
O Emphasis control signal output terminal Not used (open)
O Write frame clock signal output terminal Not used (open)
O Sub-code sync (S0+S1) detection signal output to the system controller (IC701)
O Sub-code P-W serial data output terminal Not used (open)
I Sub-code P-W serial data reading clock signal input terminal Not used (fixed at "L")
O Sub-code Q data signal output to the system controller (IC701)
I Sub-code Q data reading clock signal input from the system controller (IC701)
Function
Not used (open)
Not used (open)
Not used (open)
Not used (open)
Not used (open)
Not used (open)
Not used (open)
Not used (open)
Not used
Not used (open)
Not used (open)
Not used (open)
Not used (open)
Not used (open)
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