AOC C787 Service Manual page 13

On Screen Display Controller
The IC103 is designed for display the built-in characters or fonts onto monitor screen. The display operation is by
transforming data and control information from micro controller to RAM through a serial data interface.
Pin2 is used to control the internal oscillator frequency by DC voltage input from external low pass filter (R125, C114,
R161) and filter (R126, C115) is used to regulate the appropriate bias current for internal oscillator the resonate at
specific dot frequency.
Pin5 is input the horizontal fly back pulse, for PLL generator tracking.
Pin6 is left floating, I2C bus is enabled. Otherwise the SPI bus is enabled.
Pin7 the external data transfer through this pin to internal display registers and control registers
Pin8 the clock-input pin is used to synchronize the data transfer.
Pin10 is input the vertical flyback pulse for synchronizing the vertical position.
Pin12 is output a blanking signal to cut off external R.G.B signals of VGA while this chip is displaying characters or
windows.
Pin13, Pin14, Pin15 is used to output the OSD (B.G.R) video signal.
5-2 DEFLECTION CIRCUIT
The deflection circuit is achieved by a high performance and efficient solution IC 401 (TDA4856) for this monitor. The
concept is fully DC controllable and can be used in applications with a micro-controller solutions.
The TDA 4856 provides sync. Processing with full auto sync. capability, a flexible SMPS block and an extensive set of
geometry control facilities. Further the IC generates the drive waveforms for DC coupled vertical boosters to the TDA
4866 [ref Page-28].
Horizontal Oscillator
The oscillator is of the relaxation type and requires a capacitor of 10nF C403 at pin 29. The maximum oscillator
frequency is determined by a resistor R403 form pin 28 to ground. A resistor R402 from pin27 to pin28 defines the
frequency range.
PLL 1 Phase Detector
The phase detector is a standard one using switched current sources. It compares the middle of H-sync. with a fixed point
on the oscillator saw-tooth voltage. The PLL loop filter c401, R401, C402 is connected to Pin26.
PLL2 Phase Detector
This phase detector is similar to the PLL1 detector and compares the line flyback pulse at pin 1 with the oscillator saw-
tooth voltage. The PLL2 detector thus compensates for the delay in the external H-deflection circuit by adjusting the
phase of the HDRV output pulses. The phase between H-flyback and H-sync can be controlled at pin30.
X-ray Protection
The X-ray protection input pin2 provides a voltage detector with a precise threshold. If the voltage exceeds this threshold
for a certain time, an internal latch switches the whole IC into protection mode. In this mode several pins are forced into
defined states:
Pin7 (HDRV) is floating
Pin6 (BDRV) is floating
Pin12, 13 ( VOUT 1, 2) are floating
Pin16 (CLBL) provides a continuous blanking signal.
Vertical Oscillator
The vertical free –running frequency is determined by the resistor R608 at pin23 and capacitor C604 at pin24. Usually the
free-running frequency should be lower than the minimum trigger frequency.


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