Panasonic NV-DS30EG Service Manual page 27

VIDEO SIGNAL PROCESS II BLOCK DIAGRAM
MAIN C.B.A.
IC3201 (FORMATTING/EQUALIZER)
TO/FROM VIDEO I
80
SIGNAL PROCESS DBR (0-3)
BLOCK DIAGRAM
83
(FROM IC6001(71))
RESET(L)
(FROM IC6001(63))
XWEH
FROM SYSTEM
(FROM IC6001(64))
CONTROL
XWEL
BLOCK DIAGRAM
(FROM IC6001(62))
XRE
(FROM IC6001(61))
ADDRESS STROBE
27MHz CLOCK
24.576MHz CLOCK
TO/FROM VIDEO I ADM (0-15)
SIGNAL PROCESS
3 BLOCK DIAGRAM
DBP (0-3)
NV-DS29EG/NV-DS29EGM/NV-DS29B/NV-DS29EGE/NV-DS30EG/NV-DS30EGM/NV-DS30B/NV-DS30EGE/NV-DS30EN/NV-DS30ENT/NV-DS30ENC/NV-DS30A/NV-DS50EN/NV-DS50ENT/NV-DS50A
MODULATOR
/DEMODULATOR
AGC CONTROL
VITERBI EQUALIZER A/D CONVERTER
ATF DET BPF A/D CONVERTER
MICROCONTROLLER
INTERFACE
D/A CONVERTER
ADDRESS 27MHz
RESET(L) RESET(L) XWEH XWEL XRE STROBE CLOCK
52 54 55 57 58 61 64
30 4 78 77 74 75 88
66 68 70 73
REC VIDEO SIGNAL
IC5001 (HEAD AMP)
41 8
LOGIC DRIVE GCA
REC CLOCK 45 10
AGC
27 3
DET
AGC
AMP 8 6 1 43
AMP
AMP 5 39
REC-C CONTROL 29 35
EQ HOLD 43 11
REC CONTROL 44 15
HEAD SW PULSE 2 38 16
HEAD SW PULSE 1 36 17 LOGIC
PB(H) 42 18
REC ON/OFF CONTROL 39 19
(FROM SAFETY TAB SW)
14
S-TAB ON(L)
20
TO SYSTEM
(TO IC6001(86))
CONTROL
HEAD SW IC3202 (IEEE1394 INTERFACE)
BLOCK DIAGRAM PULSE 1
73 XWEL
71 XRE
74 ADDRESS STROBE
94 27MHz CLOCK
28 24.576MHz CLOCK
50
51
53
56
58
MICROCONTROLLER
61 INTERFACE
63
66
68
69
75 DATA (4 BIT)
76
IEEE1394
INTERFACE
79
81
27
NV-DS30EG / NV-DS30EGM / NV-DS30B / NV-DS30EGE / NV-DS30EN / NV-DS30ENT / NV-DS30ENC / NV-DS30A
PB VIDEO SIGNAL REC AUDIO SIGNAL PB AUDIO SIGNAL
CYLINDER UNIT
FP5
27
CH1 4
26
HEAD FP5
28
AMP 5
29
FP5
31
CH2 3
30
HEAD FP5
AMP AMP 32
AMP 2
33
LPF
41
B2
ENVELOPE
13
B2 TO MEASURING BOARD
HEAD SW
PULSE (FOR EVR ADJUSTMENT)
14
B2
ATF
11
REAR C.B.A.
B1 B1201
14
14 14
B1 B1201
15
15 15
B1 B1201
17
27 27
B1 B1201
18
26 26
VIDEO SIGNAL PROCESS II BLOCK DIAGRAM
CH 1
HEAD
CH 2
HEAD
JK7003
DV JACK
1 TPB(-)
2 TPB(+)
3 TPA(-)
4 TPA(+)
5 GND