FO-1850TH
(5) Image signal process block
AMPLIFIER
CLAMP
CCD
VIDEO
CIRCUIT
CIRCUIT
SIGNAL
XFC-MVP
CLOCK
VREF+
VREF–
Fig. 5
The CCD is driven by the 1-chip engine (XFC-MVP), and the output
video signal from the CCD is input into the XFC-MVP through the
amplifying circuit and clamp circuit.
The ADC and buffer are provided in the XFC-MVP, and the digital
image processing is performed.
5 – 8