Pioneer CDJ-850 Service Manual page 31

5
[10] Confirmation of basic operations of the CPU/DSP
First, check if the voltage at each section is OK.
[10-1] Periphery of the MAIN CPU: IC103
No. Cause Diagnostics Point
MAIN Assy
1 —
MAIN_CPU
(IC103)
[10-2] SERVO DSP: IC201
No. Cause Diagnostics Point
MAIN Assy
—
1
SERVO DSP
(IC201)
[10-3] AUDIO DSP: IC301
No. Cause Diagnostics Point
MAIN Assy
1 —
AUDIO DSP
(IC301)
[10-4] PANEL CPU: IC1007
No. Cause Diagnostics Point
DFLB Assy
—
1
PANEL CPU
(IC1007)
5
6
Item to be Checked
Check the waveforms and levels of the following
signals:
• MAIN_XRST: MAIN CPU releases reset with "H".
• 33 MHz OSC circuit: Oscillation circuit for
system clock.
• 48 MHz OSC circuit: Oscillation circuit for USB
clock.
• SH_STATUS: Status signal of MAIN CPU.
"H/L" pulse signal in the normal state.
• CLK66M: 66 MHz clock signal output for FLASH
ROM and SDRAM.
Item to be Checked
Check the waveforms and levels of the
following signals (in CD PLAY mode):
• SRVRST: SERVO DSP releases reset with "H".
• CLK_S_16M: 16 MHz system clock signal input.
• SRVSCLK: Communication clock signal.
Item to be Checked
Check the waveforms and levels of the
following signals (in PLAY mode):
• DSPDREQ: Communication request signal
• DSPRST: AUDIO DSP releases reset with "H".
• CLK_A_16M: 16 MHz system clock signal input.
Item to be Checked
Check the waveforms and levels of the following
signals:
• RESET(IC1007-pin 12): PANEL CPU releases
reset with "H".
• 16 MHz OSC circuit: Oscillation circuit for
system clock.
• TSCK(IC1007-pin 37): Communication clock
signal output.
CDJ-850
6
7
Corrective Action
If both the Reset and Oscillation circuits are OK, but the
SH_STATUS signal is fixed at "L" or "H" (not "H/L" pulse
signal), the Main CPU is not operating.
If the reset is not "H", following points may be defective.
• Loose connection of the reset line
• Defective part of PANEL CPU(IC1007)
• Malfunction detection of the voltage.
If both the Reset, Oscillation circuits and 66 MHz clock
signals are OK, IC103 (MAIN CPU), IC101 (FLASH ROM)
or IC102 (SDRAM) may be defective.
Corrective Action
If both the Reset and System clock signals are OK,
but the SRVSCLK signal is not output, the SERVO
DSP (IC201) may be defective.
Corrective Action
If both the Reset and System clock signals are OK,
but the DSPDREQ signal is not output, the AUDIO
DSP (IC301) may be defective.
Corrective Action
If both the Reset and Oscillation circuits are OK, but
the TSCK signal is not output, the PANEL CPU
(IC1007) may be defective.
7
8
A
Reference
10.14
WAVEFORMS
4 1
10.15 EACH
SIGNAL LEVEL
B
P
Reference
10.14
WAVEFORMS
3 6
10.15 EACH
SIGNAL LEVEL
R
C
Reference
10.14
WAVEFORMS
5 2
10.15 EACH
SIGNAL LEVEL
Q
Reference
D
10.14
WAVEFORMS
8
10.15 EACH
SIGNAL LEVEL
G
E
F
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