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3. The principle of rec/play clock generated by the PLL
The clock is reproduced by the PLL with respect to the signal
which has been detected to be the FCM signal by the circuit
(primary function circuit) which generates the slice level from
the FCM signal. The frequency of the reproduced clock is 20
MHz.
4. LC filter
LC filters are located before and after the VCA (IC853). Dur-
ing recording, there is the possibility that the WCLK (20 MHz)
or other high-frequency interference can become mixed in with
2. ADDRESS DETECTION/AMPLIFIER
Mainly the address detection of the disc and signal process in
order to detect are done.
outside
inside
C D
B A
Land
Land
Groove
Groove
IC814
(AD8054)
A, B, C, D
Main Matrix
[(A+D)-(B+C)]
1. Address detection
The main PP signal ((A+D)–(B+D)) at the tracking servo am-
plifier shown in Fig. 5 passes through the VCA circuit (IC853)
and the LPF circuit, after which the address peak signal is
input to the DSP of the ASIC (IC402) and A/D conversion is
then carried out. As a result, the maximum amplitude of the
address signal is detected and the control potential of the VCA
2-3-3. RF AMPLIFIER
RF is the data signal that it is to be read by a pickup sensor (I, J).
Gain-Amplifier
I
J
I/J is bias by 2.5 V (FREF).
The OA amplifiers, analog switch
and the power supply of the comparator
IC are all 5V.
Land
IC856
(ADG701)
IC854
(AD8054)
LC
Filter
Attenuator
Gain fixing
WG
Read: x 6.81
IC857
"0" REC
Write: x 3.78
(AD8534)
"1" PLAY
ADRSGC
Amp
SSI33P3721
x 8.17
AGC
AGC on/off
IC838
(AD8062)
MOAGCHLD
AGCOFFH
the FCM signal or the address signal. These LC filters remove
almost all of the signal components which are at 20 MHz or
above, leaving just the base frequencies (2-3 MHz) for the
FCM and address signals.
5. Peak hold for FCM signal and bottom hold circuit
These circuits use the amplitude modulation of the FCM sig-
nal to hold the peak level and the bottom level of the FCM
signal at the capacity which is connected to the transistor
emitter.
FCLKWIN
IC859
(ADG702)
VCA
variable range
Gain-Amp
(± 4dB(min))
LC
Filter
Ctrl
comparator
IC854
IC853
input allowable value
(AD8054)
(BA7655)
(0.67~3.36V)
(IC853) is changed so that the amplitude of the address sig-
nal can be changed to the appropriate level. Furthermore, it is
input to the comparator (IC852) to generate the address sig-
nal. This address signal is taken up by the DC macro of the
ASIC (IC402) to be used as the frame address and track ad-
dress during recording and playback.
Boost
Cutoff
Programmable
Equalizer
Filter
+5VA
IC836
(ADG701)
During AGC OFF
Gain is decided.
– 7 –
AS-MO ASIC
ADRSAMPL 189
PEAK HOLD
A14
CIRCUIT
ADRSGC 173
A02
Comparator
VC25
ADRSPLS 163
ADRSPLS
IC852
(LT1721)
TP801
(MO observation)
AS-MO ASIC
MO-RF
136
RF
137
IC832
REFTOP
2.0V
(AD8051)
138
1.0V
REFBTM
221
AGCOFFH
P06
Fig. 8
Fig. 9
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