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4.6
MAIN(DV MAIN) SCHEMATIC DIAGRAM
MAIN
0 1
[DVMAIN section]
TO
CAMERA DSP
R3051
100
TDA
TCMK
TMS
TDO
TRST
5
TO MAIN IF
CN110
REG_2.5V
REG_1.8V
REG_3V
GND
L3002
DIGITAL_3V
NQR0129-002X
C3003
1
L3005
DIGITAL_1.8V
NQR0006-001X
C3007
NCB10JK-106X
10
L3004
ANALOG_2.5V
NQR0006-001X
C3005
4
10
/6.3
T
L3006
ANALOG_1.8V
NQR0006-001X
C3008
10
/6.3
T
MA2Z720-X
D3004
L3001
PHY_2.85V
NQR0129-002X
C3001
10
/6.3
T
3
2
TO MAIN IF
CN107
AGC_OUT
VRB_AGC
VREF_1.1
REC_DATA
REC_CLK
REC_CTL
REF_CLK
ATFI
VRB_ATF
L3012
NQR0006-001X
C3055
1
R3041
∗
1
NOTE : The parts with marked (
A
C3047
0.1
N.C
N.C
MON0
MON1
VDDE
VDDI
MON2
MON3
MON4
MON5
VSS
MON6
MON7
MON8
MON9
MON10
C3042
0.01
MON11
MON12
C3043
VDDE
VDDI
0.01
MON13
MON14
MON15
MON16
MON17
MON18
MON19
VSS
MON20
MON21
MON22
MON23
VDDE
MON24
MON25
MON26
MON27
VDDE
C3044
0.1
N.C
VDDP
VSSP
VDDA
VSS
N.C
N.C
VDDE
VSS
VSS
VDDE
VDDI
VSS
VDDE
VDDE
VDDI
VSS
VSS
MTEST
C3045
0.1
PHYAVD2
BUSRST
RA3004
10k
PHYAVS2
PMODE
PWR3
PWR1
PWR2
VDDI
PHYAVS1
PHYAVD3
C3046
0.01
PHYAVD1
VSS
VDDE
A/D
VCO
D/A
VDDI
VSS
C3011
0.1
C3065
∗
R3029
1M
IC3002
R3034
82K
JCY0174-X
R3035
12K
C3061
R3059
0.01
R3040
VCO
10
2.2K
C3062
IC3003
0.01
∗
SN74AHC1G04K-X
R3036
1.2K
C3056
R3037
1
1.5K
C3058
0.047
∗
) is not used.
B
C
IC3001
JCY0152
[DVMAIN]
D/A
A/D
L3007
2.2µ
CH
R3009
10k
R3010
10k
R3058
10k
D
E
4-13
4-14
CPUBUSTYPE
CPUDSLOGIC
CPUWAITLOGIC
CPUWAIT
XINT
XCPUCS
XCPURW
XCPUDSTB1
XCPUDSTB0
CPUALE
INV
INH
OUTV
OUTH
BRSI3
BRSI2
BRSI1
BRSI0
YSI3
YSI2
YSI1
YSI0
BRSO3
BRSO2
BRSO1
BRSO0
YSO3
YSO2
YSO1
YSO0
AODAT0
AODAT1
VSS
AOBCK
AOLRCK
DODAT
C3038
0.1
VDDI
DOBCK
DOLRCK
C3064
∗
AIDAT0
AIDAT1
AIMCK
AIBCK
AILRCK
DIDAT
R3033
DIMCK
2.2k
DIBCK
DILRCK
C3037
6p
OSC11O
OSC11I
X3002
R3012
[24.576MHz]
0Ω
OSC24O
OSC24I
C3036
6p
VCXO12O
VCXO12I
VCXO11O
L3008
VCXO11I
12µ
C3050
C3031
0.1
0.001
VDDP
C3030
0.1
CH
VCIAUD
C3032
C3033
VCO
0.001
22p
VSSP
VDDE
D3002
D3003
PWMAUDIO
R3027
EC2C01C-X
EC2C01C-X
VSS
10k
VDDE
N.C
C3049
0.0022
LPFIN
R3045
R3046
C3048
R3028
8.2k
LPFOUT
10k
680
0.047
VDDE
PHYAVS3
PHYVSR
C3029
PHYVSA
0.01
PHYVDR
PHYVDA
C3063
∗
CH
F
TO VIDEO I/O,
CAMERA DSP
INV
INH
R3021
10
TO MSD CPU, CAMERA DSP
OUTV
R3022
10
TO CAMERA DSP
OUTH
DCO3
DCO2
DCO1
DCO0
TO VIDEO I/O,
DYO3
CAMERA DSP
DYO2
DYO1
RA3001
DYO0
100
DCI3
DCI2
DCI1
DCI0
DYI3
TO
DYI2
CAMERA DSP
DYI1
DYI0
100
CLK27A
RA3002
TO MAIN AUDIO
AODAT
AIDAT
R3006
10
AIMCK
AIBCK
AILRCK
TO MSD CPU
ADDT15
ADDT14
ADDT13
ADDT12
ADDT11
ADDT10
ADDT09
ADDT08
ADDT07
ADDT06
ADDT05
ADDT04
ADDT03
ADDT02
ADDT01
ADDT00
DV_WAIT
DRWSEL
DRE
DWE
DALE
DV_RST
CLK27SEL
SRV_TRK
TO MAIN IF
TSR
CN105, MSD CPU
FRP
SPA
HID1
TO MSD CPU
TO MAIN IF
CN105
FS_PLL
MAIN_VCO
PB_CLK
DISCRI
SBE
J101
RA3003
0
TPA+
TPA-
TPB+
DV I/O
TPB-
TO VIDEO I/O
PBPLLCTL
FSPLLCTL
M_VCOCTL
PBVCOCTL
y10360001a_rev0
G
H
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