Lsi Pin Function; Cpu - Casio BN-10 Service Manual & Parts List

Casio bn-10; bn-20 organizer
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8. LSI PIN FUNCTION

8-1. CPU (LSI1)
This CPU is COB (Chip on board). Therefore this CPU cannot be replaced for repair.
CPU:UPD3066P (NC3020)
Pin No.
Name
1 ~ 12
KO1 ~ KO12
13 ~ 20
KI1 ~ KI8
27
TCH
28
AVCC
29
VREF
30
AVSS
37
BLD1
38
BLD2
40, 41
BZ0, BZ1
43
TXD
44
RXD
46
INT0
48
NMI
53
PORT8
54
PORT7
55
PORT6
56
PORT5
57
PORT4
58
PORT3
59
PORT2
60
PORT1
61
PORT0
62
VSEL1
63
VSEL2
67
CS8B
68
CS7B
69
CS6B
70
CS5B
71
CS4B
72
CS3B
73
CS2B
74
CS1B
75
CS0B
76
WEB
77
OEBP
78
OEB
80
GND
81 ~ 103
A0 ~ A22
104
GND
105 ~ 120 D0 ~ D15
121
GND
129
SW
130
GND
131
PO
132
PI
133
VCC1
134
XO
135
XI
136
VCC2
143
RESET
I / O
O
Key scanning signals
I
Key scanning signals
I
Signal to CPU for the start of data transfer between PC and BN Unit
I
Power supply to A/D converter of CPU
I
Reference voltage terminal for A/D converter
Ground for A/D converter of CPU
I
Signal to CPU for detection of low battery (2.1 V)
I
Signal to CPU for detection of forced power off (1.6 V)
O
Terminals for drive of buzzer
O
Terminal for serial data transfer (both PC LINK and MODEM)
I
Terminal for serial data transfer (both PC LINK and MODEM)
I
Interrupt signal from Gate array to CPU
I
Non maskable interrupt signal from Gate array (LSI2) to CPU
O
Display ON/OFF signal from CPU to LCD driver LSI
I
Signal to CPU for selection of BN Units (BN-10: no EL)
I
Signal to CPU for control of external port for MODEM
O
Signal to EL driver IC for control (power ON/OFF) of backlight
O
Control signal for power supply to LCD (power ON/OFF)
I
Wait signal from Gate array (LSI2)
O
RESET signal to flash ROM (LSI304 and LSI306)
I
Ready/Bussy signal from flash ROM (LSI304, 306, 308)
O
RESET signal to Gate array (LSI2) and flash ROM (LSI308)
I
Power supply (5 V) to CPU
I
Power supply (3 V) to CPU
O
not used
O
Chip select signal to MASK ROM (LSI301) and LSI308
O
Chip select signal to LSI for MODEM passing trough Gate array
O
Chip select signal to flash ROM (LSI304)
O
Chip select signal to flash ROM (LSI306)
O
Control signal to data latch IC (IC151) for control of power supply to LCD
O
Chip select signal to LSI (LSI4, 5) for LCD segment driver
O
Chip select signal to Gate array (LSI302)
O
Chip select signal to RAM (LSI303)
O
Write enable signal to LSI for memory and Gate array
O
Clock (10MHz) to Gate array
O
Output enable signal to LSI for memory and Gate array
Ground for CPU
O
Address bus terminals
Ground for CPU
I/O
Data bus terminals
Ground for CPU
I
Signal from battery cover switch to CPU
Ground for CPU
O
Terminal for system clock (10.14 MHz)
I
Terminal for system clock (10.14 MHz)
I
Power supply to logic and oscillator circuit of CPU (2.2 V)
O
Terminal for oscillator circuit of interior clock (32.768 kHz)
I
Terminal for oscillator circuit of interior clock (32.768 kHz)
I
Power supply to buzzer and keys
I
Reset terminal to CPU (from P key)
— 41 —
Function

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