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SDR_BA[1:0]
Output
SDR_DQ[31:0]
I/O
SDR_RASZ
Output
SDR_CASZ
Output
SDR_WEZ
Output
SDR_DQM[3:0]
Output
SDR_MCLKO
Output
SDR1_CKE
Output
SDR1_AD[11:0
Output
]
SDR1_BA[1:0]
Output
SDR1_DQ[15:0
I/O
]
SDR1_RASZ
Output
SDR1_CASZ
Output
SDR1_WEZ
Output
SDR1_DQM[1:0
Output
]
SDR1_MCLKO
Output
TS Input Interface
TSCLK
Input
TSDATA[7:0]
Input
TSVALID
Input
TSSYNC
Input
SDRAM Bank Select
SDRAM Data Bus
SDRAM Row Address Strobe; active low
SDRAM Column Address Strobe; active
low
SDRAM Write Enable
SDRAM Data Mask for Low Byte; active
high
Master Clock Output to SDRAM
SDRAM1 Clock Enable
SDRAM1 Address Bus
SDRAM1 Bank Select
SDRAM1 Data Bus
SDRAM1 Row Address Strobe; active
low
SDRAM1 Column Address Strobe;
active low
SDRAM1 Write Enable
SDRAM1 Data Mask for Low Byte;
active high
Master Clock Output to SDRAM1
TS Clock
TS Data in Parallel; LSB (bit 0) is
for serial TS data
TS Data Valid
TS Sync-Byte Indicator
129,
130
168-
161,
157-
150,
124-
117,
114-
107
131
132
133
169,
149,
125,
106
128
225
224-
213
233,
232
251-
245,
243,
242,
240-
234
231
230
227
229,
228
226
95
96-1
03
104
105
12
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