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LVB2M
Output
LVB2P
Output
LVBCKM
Output
LVBCKP
Output
LVB3M
Output
LVB3P
Output
Internal MCU Interface with Serial Flash Memory
SAR3
Analog Input
SAR2
Analog Input
SAR1
Analog Input
SAR0
Analog Input
SCK
Output
SDI
Output
Input w/
SDO
5V-tolerant
CSZ
Output
GPIO_P10-GPI
I/O w/
O_P17
5V-tolerant
I/O w/
UART_TX
5V-tolerant
I/O w/
UART_RX
5V-tolerant
Input
IRIN
w/5V-toleran
t
INT
Input
SCLM
Output
I/O w/
SDAM
5V-tolerant
DDC_SCL
I/O
DDC_SDA
I/O
DDC_ROMSCL
I/O
DDC_ROMSDA
I/O
SDRAM Interface
SDR_CSZ
Output
SDR_CKE
Output
SDR_AD[11:0]
Output
LVDS B-Link Channel 2 Negative Data
Output
LVDS B-Link Channel 2 Positive Data
Output
LVDS B-Link Negative Clock Output
LVDS B-Link Positive Clock Output
LVDS B-Link Channel 3 Negative Data
Output
LVDS B-Link Channel 3 Positive Data
Output
SAR Low Speed ADC Input 3
SAR Low Speed ADC Input 2
SAR Low Speed ADC Input 1
SAR Low Speed ADC Input 0
SPI Interface Sampling Clock
SPI Interface Data-In
SPI Interface Data-Out
SPI Interface Chip Select
General Purpose Input/Output; 4mA
driving strength
Universal Asynchronous Transmitter
Universal Asynchronous Receiver
IR Receiver Input
MCU Bus Interrupt; 4mA driving
strength
I2C Master Clock
I2C Master Data
DDC Clock for D-SUB Input
DDC Data for D-SUB Input
DDC ROM Clock for D-SUB Input
DDC ROM Data for D-SUB Input
SDRAM Chip Select; active low
SDRAM Clock Enable
SDRAM Address Bus
195
194
190
189
188
187
204
203
202
201
171
172
173
174
41-4
8
55
56
57
58
59
60
33
34
35
36
134
126
148-
137
11
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