Vizio VM60P HDTV10A Service Manual page 61

TMDS digital core
The two TMDS cores perform 10-to-8-bit TMDS decoding on the audio and video data
received from the three TMDS differential data lines along with a TMDS differential clock. The
TMDS cores can sense a stopped clock or stopped video and put the receiver into
power-down mode.
Active Port Detection and Selection
Only one port may be active at a time, under control of the receiver's firmware. Active TMDS
signaling may arrive at both ports, but only one will have its TMDS clock pair termination
active and only one port will have its internal circuitry enabled. These states are controlled
with register settings by the firmware in the display.
Other control signals are associated with the TMDS signals on each HDMI port. The +5V
supply from each attached host can be monitored by the SiI9025. The microcontroller can poll
registers to check on which ports are connected. The firmware also controls functional
connection to one of the two E-DDC buses, enabling one while disabling the other. An
attached host determines the active status of an attached HDMI device by polling the E-DDC
bus to the receiver.
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