Vizio VM60P HDTV10A Service Manual page 52

LVDS Transmitter
Two LVDS channels (A and B) are available on the output of the FLI8668 to transmit data and
timing information to the display device.
FLI8668 directly drives the standard LVDS interface panels, supporting all standard data
formats—single and dual bus, 18- or 24-bit data output. The 24-bit data may be mapped as
either standard receiver formats. The following diagrams illustrate the RGB, HSync, VSync
and Data Enable signal mapping in a single bus output configuration. For dual bus output, the
only difference is that the even bus contains only the "even" pixels and the odd bus contains
only the "odd" pixels with the data clock at DCLK/2.
The following diagram shows the available LVDS mapping for 8-bit LVDS output which is
applying to PDP panel spec:
8-bit LVDS Output
Figure 8-6 Data Mapping For LVDS Output In 8-BIT Configuration With EIGHT_BIT_MODE_SEL=0
Figure 8-7 Data Mapping For LVDS Output In 8-BIT Configuration With EIGHT_BIT_MODE_SEL=1
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