Vizio VM60P HDTV10A Service Manual page 58

Display output interface
The Display Output Port provides data and control signals that permit the FLI8668 to connect
to a variety of display devices using a TTL or LVDS interface. The output interface is
configurable for single wide LVDS in 18, 24, or 30-bit RGB pixel format in single or
double-wide formats. TTL output is available in 18 or 24-bit RGB pixel formats as well as 20
and 24 4:2:2 YUV single wide formats. All display data and timing signals are synchronous
with the DCLK output clock. The integrated LVDS transmitter is programmable to allow the
data and control signals to be remapped to support all common LVDS receiver formats. DC
balanced operation is supported as described in the Open LDI standard.
Note: If the output is 4:4:4, the width can be 30 bits (10 bit per channel) or 24 bits (8 bits per
channel) and YUV is re-mappable through the 3x3 matrix. If the output is 4:2:2, the 3x3 matix
can only be used for color space conversion and there are three fixed options:
a. 4:2:2, 8 bits per channel, outputs allocation – G = Y, B = UV
b. 4:2:2, 10 bits per channel, outputs allocation – G = Y, B = UV
c. 4:2:2, 12 bits per channel, outputs allocation – G [7:0] = Y [11:4], B [7:0] = UV [11:4], R [3:0]
= UV [3:0], R [7:4] = Y [3:0]
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