Vizio VM60P HDTV10A Service Manual page 48

Clock Generation
The FLI8668 features six clock inputs. All additional clocks are internal clocks derived from
one or more of these:
1.Crystal Input Clock (TCLK and XTAL). This is the input pair to an internal crystal oscillator
and corresponding logic. A 19.6608MHz TV crystal is recommended for best noise immunity
with the 3D decoder. Alternatively, a single-ended TTL/CMOS clock oscillator can be driven
into the TCLK pin (leave XTAL as N/C in this case). If an external crystal is being used,
connect a 10K pull-up to OCMADDR_19. See Figure 8-3 Resetn Ball Behavior.
2.Digital Input Video/Graphics Clocks (IPCLK0, IPCLK1, IPCLK2 and IPCLK3)
3.Audio Delay Clock (AVS_CLK)
The FLI8668 TCLK oscillator circuitry is a custom-designed circuit to support the use of an
external oscillator or a crystal resonator to generate a reference frequency source for the
FLI8668 device.
CONFIDENTIAL – DO NOT COPY
Figure 8-3 Resetn Ball Behavior
Page 8-3
File No. SG-0214