Sony HCD-CP500MD Service Manual page 64

HCD-CP500K/CP500MD
• IC151 CXD2662R DIGITAL SIGNAL PROCESSOR, DIGITAL SERVO SIGNAL PROCESSOR (BD BOARD)
Pin No. Pin Name
1 MNT0 (FOK)
2 MNT1 (SHCK)
3 MNT2 (XBUSY)
4 MNT3 (SLOC)
5 SWDT
6 SCLK
7 XLAT
8 SRDT
9 SENS
10 XRST
11 SQSY
12 DQSY
13 RECP
14 XINT
15 TX
16 OSCI
17 OSCO
18 XTSL
19 DIN0
20 DIN1
21 DOUT
22 DADTI
23 LRCKI
24 XBCKI
25 ADDT
26 DADT
27 LRCK
28 XBCK
29 FS256
30 DVDD
31 to 34 A03 to A00
35 A10
36 to 40 A04 to A08
41 A11
42 DVSS
43 XOE
44 XCAS
45 A09
46 XRAS
47 XWE
* I (S) stands for Schmidt input, I (A) for analog input, O (3) for 3-state output, and O (A) for analog output in the column I/O
64
I/O
Function FOK signal output to the system control (monitor output)
O
"H" is output when focus is on (Not used)
O Track jump detection signal output to the system control (monitor output)
O Monitor 2 output to the system control (monitor output)
O Monitor 3 output to the system control (monitor output) (Not used)
I Writing data signal input from the system control
I (S) Serial clock signal input from the system control
I (S) Serial latch signal input from the system control
O (3) Reading data signal output to the system control
O (3) Internal status (SENSE) output to the system control
I (S) Reset signal input from the system control "L": Reset
Subcode Q sync (SCOR) output to the system control
O
"L" is output every 13.3 msec. Almost all, "H" is output
O Digital In U-bit CD format or MD format subcode Q sync (SCOR) output to the system control
I Laser power switching input from the system control "H": Recording, "L": Playback
O Interrupt status output to the system control
I Recording data output enable input from the system control
I System clock input (512Fs=22.5792 MHz)
O System clock output (512Fs=22.5792 MHz) (Not used)
I System clock frequency setting "L": 45.1584 MHz, "H": 22.5792 MHz (Fixed at "H")
I Digital audio input (Optical input)
I Digital audio input (Optical input) (Fixed at "L")
O Digital audio output (Optical output) (Open)
I Serial data input (Fixed at "L")
I LR clock input "H" : Lch, "L" : R ch (Fixed at "L")
I Serial data clock input (Fixed at "L")
I Data input from the A/D converter
O Data output to the D/A converter (Not used)
O LR clock output for the A/D and D/A converter (44.1 kHz) (Not used)
O Bit clock output to the A/D and D/A converter (2.8224 MHz) (Not used)
O 11.2896 MHz clock output (Not used)
— +3V power supply (Digital)
O DRAM address output
O DRAM address output (Not used)
O DRAM address output
O DRAM address output (Not used)
— Ground (Digital)
O Output enable output for DRAM
O CAS signal output for DRAM
O Address output for DRAM
O RAS signal output for DRAM
O Write enable signal output for DRAM
Description