NOTE: This diagram is for reference only. It may not be accurate for all machines covered by this manual.
ELECTRICAL DIAGRAMS
J7
6
C94
C107
J7
C105
C93
C109
C106
7
38
VSTDBY
1uF
1uF
35V
35V
0.1uF
0.1uF
0.1uF
0.1uF
C95
J7
1
0.1uF
D
+5V
J7
15
+15V
R8
J7
14
C119
C110
C120
C108
22.1K
J6
16
0.1uF
0.1uF
22uF
22uF
20V
20V
J6
8
+15V
D
C12
NOISE_GND
R81
R88
C13
J4
7
4.7uF
11
475
35V
475
C43
120uF
R87
50V
NOISE_GND
10.0K
J6
7
820pF
C135
C14
J6
6
1uF
0.1uF
J6
D
14
J6
15
+5V
NOISE_GND
J1
/RES
7
C136
C11
/BERR
J1
6
J1
FREEZE
1uF
0.1uF
5
J1
/BKPT
13
/DS
J1
14
J1
15
D3
D
J6
9
FPGA_RESET
(4)
S1G
FPGA_DONE
(4)
J6
2
RMC
(4)
/AS
2
(4)
IRLR120N
/DS
(4)
Q9
OUTPUT_ON
10A,100V
(4)
3
SYS_RESET
(2,3,4)
FPGA_INT
(4)
NOISE_GND
INT_CAN
(2)
FPGA_BAD
(4)
+5V
J6
12
FAULT
IRLR120N
SIGNAL
Q10
C67
C73
C68
RED
LED7
D
10A,100V
0.1uF
0.1uF
0.1uF
+5V
R183
750
D
D
D
+5V
+5V
J1
3
R174
X17
J1
8
(4)
43
GCK1
J1
9
(3,4)
44
GCK2
(3,4)
1
11
J1
GCK3
TCK
11
(4)
36
10
GTS1
TMS
(4)
34
9
GTS2
CPLD
TDI
J1
10
(4)
33
24
GSR
TDO
(4)
MISO7
40
39
(4)
(2)
IO1A
IO1B
41
38
(2)
IO2A
IO2B
42
37
RESET_RAMP
IO4A
IO4B
(3)
STROBE_AD
32
2
IO6A
IO7B
(3)
CAPB_UV
3
31
IO8A
IO8B
CAPB_OV
D
5
30
IO9A
IO9B
CLR_CAP
6
29
(3)
IO10A
IO10B
CMP0
7
28
(4)
IO11A
IO11B
8
27
CMP2
(4)
IO12A
IO12B
CRYSTAL
12
23
IO13A
IO13B
OUTPUT_ON
13
22
IO14A
IO14B
SOFTST
14
21
IO15A
IO15B
16
20
IO16A
IO16B
DISABLE_455
18
19
(4)
IO17A
IO17B
D
D
+5V
+5V
X24
84
VDDSYN
R170
25
VDDE
10.0K
26
VSSE
R171
1
MC68332
1.00K
R172
10.0K
R90
CAP1
(2,4)
X10
9
8
1.00K
C44
C143
4700pF
+5V
330pF
D
+5V
X10
X30
3
10
3
4
1
R179
Q19
3.32K
3
X23
2
C104
2
VDD
1
1
RES'
Q20
VSS
MMBT4401
1uF
3
S80746AN
35V
2
4.6V/2%
PWRDN_INT
D
D
/RES
R/W
+5V
(3)
(2)
+5V
X30
10.0K
11
10
R254
X24
CRYSTAL
85
87
EXTAL
XFC
83
90
CLK
(1,4)
XTAL
CLKOUT
140
/CSB
/RES
92
CSBOOT'
RESET'
141
/CS0
93
BR'
CS0'
/
HALT'
142
/CS1
BG'
/
CS1'
TSC
80
143
/CS2
TSC
BGACK'
/
CS2'
/BERR
94
77
/IPIPE
BERR'
IPIPE'
/
DSO
FREEZE
81
78
/IFETCH
FREEZE
IFETCH'
/
DSI
/BKPT
79
103
R/W
BKPT' /DSCLK
R/W
FPGA_RESET
114
DSACK0' /PE0
115
FPGA_DONE
113
A0
DSACK1'
/PE1
39
ADDR1
LEVEL_IN
112
A1
AVEC'
/PE2
40
ADDR2
RMC
111
A2
RMC'
/PE3
41
ADDR3
J1
/AS
106
A3
12
AS'
/PE4
42
ADDR4
/DS
110
A4
DS'
/PE5
43
ADDR5
J1
SOFTST
105
A5
4
SIZ0
/PE6
44
ADDR6
MN_CNT
104
A6
SIZ1
/PE7
45
ADDR7
A7
46
ADDR8
OUTPUT_ON
102
A8
PF0 MODCLK
/
49
ADDR9
SYS_RESET
101
A9
PF1
/
IRQ1'
50
ADDR10
PWRDN_INT
100
A10
PF2
/
IRQ2'
51
ADDR11
FAULT_INT
99
A11
PF3
/
IRQ3'
52
ADDR12
FPGA_INT
98
A12
PF4
/
IRQ4'
56
ADDR13
INT_CAN
97
A13
PF5
/
IRQ5'
57
ADDR14
FPGA_BAD
96
A14
PF6
/
IRQ6'
58
ADDR15
INT_100
95
A15
(4)
PF7
/
IRQ7'
60
ADDR16
A16
63
ADDR17
13
A17
T2CLK
64
ADDR18
TPU0
34
A18
TPUCH0
6
ADDR19
TPU1
33
PC3/
CS6'
/
A19
TPUCH1
7
DSP_RESET
(4)
TPU2
32
PC4/
CS7'
A20
/
TPUCH2
8
VPP_CTRL
TPU3
31
PC5/
CS8'
A21
/
TPUCH3
9
IACK
(3)
TPU4
30
PC6/
CS9'
/
A22
TPUCH4
10
CAN_CS
(2)
TPU5
29
CS10'
A23
/
TPUCH5
TPU6
28
3
TPUCH6
PC0/
CS3'
FC0
/
27
4
FPGA_CS
(3)
TPUCH7
PC1/
CS4'
FC1
/
24
5
FUNCEN
(4)
TPUCH8
PC2/
CS5'
/
FC2
23
TPUCH9
22
139
DATA0
+5V
TPUCH10
D0
21
138
DATA1
TPUCH11
D1
17
137
DATA2
TPUCH12
D2
16
136
DATA3
TPUCH13
D3
15
133
DATA4
TPUCH14
D4
14
132
DATA5
TPUCH15
D5
131
DATA6
D6
MISO
65
130
DATA7
PQS0 /MISO
D7
MOSI
66
127
DATA8
PQS1
/MOSI
D8
SCK
67
125
DATA9
PQS2
/SCK
D9
SPI_CS0
68
124
DATA10
PQS3
/PCS0/ SS'
D10
SPI_CS1
69
122
DATA11
PQS4
/PCS1
D11
SPI_CS2
70
119
DATA12
PQS5
/PCS2
D12
SPI_CS3
71
118
DATA13
PQS6
/PCS3
D13
RS232_TXD
75
117
DATA14
PQS7
/TXD
D14
RS232_RXD
76
116
DATA15
RXD
D15
MC68332PV
THIS SHEET CONTAINS PROPRIETARY INFORMATION OWNED BY THE LINCOLN ELECTRIC COMPANY AND IS NOT TO BE REPRODUCED, DISCLOSED OR USED WITHOUT THE EXPRESS WRITTEN PERMISSION OF THE LINCOLN ELECTRIC COMPANY, CLEVELAND, OHIO U.S.A.