Pioneer PDP-R03U Service Manual page 130

1
• Pin Function
Pin No. Pin Name
A 1 CLPO
2 ADIN
3 RB
4 ADVS
5 ADVD
6 RT
7 ACO
8 DAVD
9 AYO
10 DAVS
B 11 VG
12 VRF
13 IRF
14 VB
15, 28 TEST
32, 33, 35, TEST
16, 27, 34 DVDD
18,23-26,29,36 DVSS
17 MOD2
19 MOD1
20 VEH3
21 VEH2
C
22 VEH1
30 APCN
31 TRAP
37 FIN
38 CKSL
39 PLSL
40 MCKO
41 ADCK
42 CPO
D
43 PLVS
44 VCV
45 PLVD
46 CLVD
47 CLPEN
48 CLVS
E
F
130
1
2
I/O
O Built-in clamp circuit current output terminal. To be connected to ADIN when built-in
clamp is used.
I Comb filter analog input (A/D converter) terminal.
O A/D converter reference bottom voltage. (standard 0.52V)
— A/D converter analog grounding terminal.
— A/D converter analog power terminal. (5.0V)
O A/D converter reference top voltage. (standard 2.6V)
O Analog chroma signal output terminal. Resistance to be added between this pin and
GND (DAVS) for obtaining the output.
— D/A converter analog power terminal. (5.0V)
O Analog luminance signal output terminal. Resistance to be added between this pin and
GND (DAVS) for obtaining the output.
— D/A converter analog grounding terminal.
O D/A converter terminal.
I Y,C ch D/A converter output full-scale setting terminal.
O x16 resistance to be connected against D/A converter output resistance "R".
O D/A converter terminal.
I Test terminal. Usually fixed at Low.
I Test terminal. Usually open or fixed at Low.
— Digital power terminal. (5.0V)
— Digital grounding terminal.
I Y/C separation mode setting terminal.
MOD2 MOD1
I L L
H L
I Vertical contour enhancement setting terminal.
I VEH3 VEH2 VEH1: Presettable in 8 steps from LLL(Off) to HHH(Max).
I
I Horizontal aperture correction circuit setting terminal. L: off, H: on
I Trap filter circuit setting terminal. L: off, H: on
I Clock input terminal. Burst lock (4fsc) to be fed in with built-in PLL system. Burst-
locked 4fsc signal to be fed in when PLL is not used.
I PLL control terminal.
L : PLL not used. FIN input clock (4fsc) to be fed in.
H : PLL used. VCO oscillator output's 4fsc clock to be fed in.
I FIN input fsc to be selected. L: fsc input, H: 2fsc input.
Either at L or H when 4fsc is fed in PLL (without built-in PLL).
O Clock (4fsc) output terminal.
I A/D converter clock input terminal. To be connected to MCKO.
O PLL phase comparator output terminal. Open when PLL is not used.
— PLL analog grounding terminal.
I VCO control voltage input terminal. To be connected to PLVS when PLL is not used.
— PLL analog power terminal. (5.0V)
— Clamp D/A converter analog power terminal. (5.0V)
I Clamp circuit enable terminal. L: Clamp on, H: Clamp off
— Clamp D/A converter analog grounding terminal.
PDP-R03U
2
3
Pin Function
Most suitable process
BPF separation mode
3
4
4