MICOM DATA MM74HC4051 8-CHANNEL ANALOG MULTIPLEXER GENERAL DESCRIPTION The MM74HC4051, MM74HC4052 and MM74HC4053 Multiplexers are digitally controlled analog switches implemented in advanced silicon-gate CMOS technology. These switches have low “on” resistance and low “off” leakages. They are bidirectional switches, thus any analog input may be used as an output and vice-versa.
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CONNECTION DIAGRAMS PHYSICAL DIMENSIONS (Pin Assignments for DIP, SOIC, SOP and TSSO) inches (millimeters) unless otherwise noted Top View TRUTH TABLES Input “ON” Channel None LOGIC DIAGRAMS...
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74LV164 8-bit SERIAL-IN / PARALLEL-OUT SHIFT REGISTER PIN CONFIGURATION FEATURES – Wide operating voltage: 1.0 to 5.5V – Optimized for Low Voltage applications: 1.0 to 3.6V – Accepts TTL input levels between V =2.7V and V =3.6V – Typical V (output ground bounce) <...
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SO14 : AD7819 2.7V to 5.5V, 200 kSPS 8-bit SAMPLING ADC plastic small outline package; 14 leads; body width 3.9 mm FEATURES – 8-Bit ADC with 4.5 µs Conversion Time – On-Chip Track and Hold – Operating Supply Range : 2.7V to 5.5V –...
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ABSOLUTE MAXIMUM RATINGS* PIN FUNCTION DESCRIPTION to DGND ..........................-0.3V to + 7V Pin No. Mnemonic Description Reference Input, 1.2V to V Digital Input Voltage to DGND (CONVST, RD, CS) .......................-0.3V, V + 0.3V Analog Input, 0V to V Analog and Digital Ground. Digital Output Voltage to DGND (BUSY, DB0-DB7) .........................-0.3V, V + 0.3V...
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AK4524 24 bit 96kHz AUDIO CODEC BLOCK DIAGRAM GENERAL DESCRIPTION The AK4524 is a high performance 24bit CODEC for the 96kHz recording system. The ADC has an Enhanced Dual Bit architecture with wide dynamic range. The DAC uses the new developed Advanced Multi Bit architecture and achieves low outband noise and high jitter tolerance by use of SCF(switched capacitor filter) techniques.The AK4524 has an input PGA and is well suited MD, DVTR system and musical instruments.
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PACKAGZ ADSP-21065L DSP MICROCOMPUTER SUMMARY – High Performance Signal Computer for Communications, Audio, Automotive, Instrumentation and Industrial Applications – Super Harvard Architecture Computer (SHARC ® ) Four Independent Buses for Dual Data, Instruction, and I/O Fetch on a Single Cycle –...
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Multiprocessing PIN DESCRIPTIONS – Distributed On-Chip Bus Arbitration for Glueless, Parallel Bus Connect Between Two ADSP-21065Ls ADSP-21065L pin definitions are listed below. Inputs identified as synchronous (S) must meet timing Plus Host requirements with respect to CLKIN (or with respect to TCK for TMS, TDI). Inputs identified as –...
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Type Function Type Function access. The ADSP-21065L deasserts ACK as an output to add wait states to access. The ADSP-21065L deasserts ACK as an output to add wait states to a synchronous access of its IOP registers. In a multiprocessor system, a a synchronous access of its IOP registers.
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CLOCK SIGNALS Type Function Test Mode Select (JTAG). Used to control the test state machine. TMS has a 20kΩ internal pull-up resistor. The ADSP-21065L can use an external clock or a crystal. See CLKIN pin description. You can configure the ADSP-21065L to use its internal clock generator by connecting the necessary components to CLKIN and Test Data Input (JTAG).
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208-LEAD MQFP PIN CONFIGURATION 208-LEAD MQFP PIN Pin Pin No. Name Name Name Name Name 127 DATA28 169 ADDR17 RFS0 SDWE DATA3 128 DATA29 170 ADDR16 DATA4 129 GND 171 ADDR15 RCLK0 DATA5 130 VDD 172 VDD DR0A SDCKE 131 VDD 173 ADDR14 DR0B SDA10...