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vector ZCB Single Board Computer
III.
THEORY OF OPERATION
3.1
System Operation Block Diagram
Since the ZCB combines the circuitry normally found on three different
S-lOO boards, its operation is somewhat complex.
In order to make the
theory of operation a bit easier to follow, we are first including a block
diagram of the major circuit areas of the
ZCB
to get an idea of the overall
system operation.
This explanation will be followed by an area by area
breakdown.
Sheet O-System Block Diagram
When the system is initially turned on the
RESRI'
block (sheet 4) pulls the
POC
line ION to let the system knON that a reset condition exists.
When the
system has already been in an on condition, the PRESEr line going low will
also cause it to issue the POC signal.
On
board, a reset condition will
cause the processor to go through a reset.
It also causes Memory Control to
issue a phantom.
When the MEMORY CONTROL block (sheet 4) is given a RESET it issues the
Phantom signal which disables all merrory on the S-lOO bus.
If
enabled, the
block will cause the first three bytes of the on-board PRCM .to be addressed.
Normally, these first three bytes are a jump to instruction which causes the
rest of the rronitor program to be run.
During normal operation, the memory
control block reads the address lines during an address cycle to determine
whether any of the on board PRCM or
RAM
is being addressed.
The jumpers in
this seciton permit the use of lK, 2K or 4K EPRCM.
The MEMORY block (sheet
5)
contains the on-board PROM and
RAM.
It is
controlled fram memory control, the S-lOO system control bus (via the S-lOO
interface block) or the
cpu.
The CLOCKS and
CLOCK
DRIVERS blocks (sheet
6)
generate the timing signals
required by the
cpu
and the system.
The clock can supply a 4MHz or a 2MHz
clocking signal, jumper selectable.
Even though not necessary with the Z-80
microprocessor, a phase 2 clock signal is generated to maintain
compatabili ty with S-lOO equipment designed to
be
used with the 8080.
The
clocks block also supplies the base signals (2MCLK and SERCLK) which are
divided down to supply all RS-232 baud rates.
The PROCESSOR block (sheet
1)
is the heart or, rrore properly, the brain of
the entire microcomputer system.
It regulates all processes, addressing,
inputs and outputs.
On
board all address and data signals are sent over MaS
level data and address buses.
All off board addressing and data
communication is done via the S-lOO interface block.
S-100 INTERFACE block and the CONTROL SIGNAL BUFFERS block (sheet
8)
consist of a number of gates which take processor signals and convert them
to system signals.
That is, many of the signals required by the system are
not generated directly fran the
Z-80.
The signals required by the system
that are not available directly are synthesized by the ZCB board.
The
Rev. 1-B
6/11/80
3-1
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