Kenwood TK-3302 Service Manual page 10

TK-3302/3302
■ Audio Amplifi er Circuit
The demodulated signal from IC201 goes to AF amplifi er
through IC308.
The signal then goes through an AF volume control , and
is routed to an audio power amplifi er (IC309) where it is am-
plifi ed and output to the speaker.
■ Squelch
Part of the AF signal from the IC enters the FM IC (IC201)
again, and the noise component is amplifi ed and rectifi ed by
a fi lter and an amplifi er to produce a DC voltage correspond-
ing to the noise level.
The DC signal from the FM IC goes to the analog port
of the MCU (IC306). IC306 determines whether to output
sounds from the speaker by checking whether the input
voltage is higher or lower than the preset value.
To output sounds from the speaker, IC306 sends a high
signal to the AF_CONT line and turns IC309 on through
Q312, Q313, Q314, Q315 and Q316. (See Fig. 4)
IC201: FM IF
IF amp
SIGNAL
DTMF
QT/DQT
BUSY QT/DQT IN
IC306 CLK, DATA,
STD, LOADN
MCU
AF_CONT
Fig. 4 AF amplifi er and squelch
■ Receive Signaling
• QT/DQT
The output signal from FM IC (IC201) enters the MCU
(IC306) through IC308. IC306 determines whether the QT or
DQT matches the preset value, and controls the SP MUTE
and the speaker output sounds according to the squelch re-
sults.
• MSK (Fleet Sync)
The MSK input signal from the FM IC goes to pin 31 of IC
308. The signal is demodulated by MSK demodulator in IC
308. The demodulated data goes to the MCU for process-
ing.
• DTMF
The DTMF input signal from the FM IC (IC201) goes to
IC308. The decoded information is then processed by the
MCU.
10
U /3306
( )
CIRCUIT DESCRIPTION
IC308
AQUA-L
IC309
AF PA Q315,316
SW
SW
Q312,313,314
3. PLL Frequency Synthesizer
The PLL circuit generates the fi rst local oscillator signal
for reception and the RF signal for transmission.
■ PLL
The frequency step of the PLL circuit is 5 or 6.25kHz.
A 12.8MHz reference oscillator signal is divided at IC1 by
a fi xed counter to produce an oscillator (VCO) output signal
which is buffer amplifi ed by Q3 then divided in IC1 by a pro-
grammable counter. The divided signal is compared in phase
with the 5 or 6.25kHz reference signal from the phase com-
parator in IC1. The output signal from the phase comparator
is fi ltered through a low-pass fi lter and passed to the VCO
to control the oscillator frequency. (See Fig. 5)
■ VCO
The operating frequency is generated by Q5 in transmit
mode and Q4 in receive mode. The oscillator frequency is
controlled by applying the VCO control voltage, obtained
from the phase comparator, to the varactor diodes (D4 and
D8 in transmit mode and D3 and D6 in receive mode).
The RX_SW pin is set high in receive mode causing Q7
turn on. The TX_SW pin is set high in transmit mode. The
outputs from Q4 and Q5 are amplifi ed by Q9 and sent to the
RF amplifi ers.
SP
■ Unlock Detector
If a pulse signal appears at the LD pin of IC1, an unlock
condition occurs, and the DC voltage obtained from C4 and
Q1 causes the voltage applied to the MCU to go low. When
the MCU detects this condition, the transmitter is disabled,
ignoring the push-to-talk switch input signal.
LPF
LPF
PLL DATA
REF OSC
X1
12.8MHz
Q5
D4,8 TX VCO
Q9
BUFF AMP
Q4
D3,6 RX VCO
Q7,8
T/R SW
5 or 6.25kHz
1/N
Phase Charge
comparator pump
1/M
5 or 6.25kHz
Fig. 5 PLL circuit
Q3
BUFFER
Q11
RF AMP
RX
TX
IC1
PLL IC