Description Of Each Block - Sharp CE-E Service Manual

-
CE-1600E

9. Description of each block

9-1. LR38045 gate array
Table-1 describes the gate array internal blocks and port addresses
(see block diagram [Fig.2]).
Block name
Bu
Bidirectional 8- bit 10 buffer.
(8-bit inputoutput buffer)
Mu
Data i1 FF1, FF2, FF3, or PA Port are sent from
(Multiplexer)
the gate array.
FF1-FF3
FF1: FF1 output is used to control the interrupt
(8-bit latch)
circuit. For instance, '1' in a bit
FF2:
FF3:
DC1-3
DC1: 32KB ROM c~ select (CSNO)
(Decoder)
DC2: 2.5' FDD select signal (I07N)
DC3: FF1- - - FF3 and FDD reset latch select
during data write.
FF1- - -FF3 and PA port select during
data read.
INT
Ths signal is OOedwi1ha PA POrt (PAOI- - -61)
(Interrupt circuits)
i1put to be sUppliedto IRQas an
As PA01---61
FF1, the interrupt becomes valid when '1' is
established for FFI.
(The interrupt equivelent circuit is shown in
[Fig.3J. )
ri
~ I~
OO~
0'
02
OS
O'
Q5
Q6
'--
RST
An input of the reset signal on RSTI resets
(Reset circuit)
FF1- - -3. At the same time, RSTN is issuedto
the 2.5" FDD reset line and remains issued until
the reset signa is canceled soltwarewise.
It is
possble
ve of the i1put to RSTI.
Reset eQuivaientcircuit is sOOwnin [Fig,4] andits
timings in [Fig. 5], )
Description
nternet
signa,
correspond wi1h 00---06
.
, RO
~
PAO I
~
PA I J
PA2 I
PA3t
V"
PA. I
"""
PAS I
A.
PA61
-t'"
?1",+-tv'J
[Fig.3J Interrupt circuit
to output RSTNsoftwarewiserrespecti
Block name
Reset line capacitor
.P""' ~ J~"OO : :.~
'RESET SW
IlI>Il· ~ '
'';TE.
(PC-1600J:1)
W-, Tt_
Reset signal, ~
F~'~~
of
NOTE: Port PA, PB, PC are all active high inside the gate array,
but converted into active low outside the gate array (see
the figure below).
ACTIVE
For instance, "1" on 00 of FF2 sets the PBON output low.
-4-
Description
VCC~
/'
RST' ~
{
t>
1 I
I ;
:0 .FFI-3RESET'
-----
--- -----
'---- - ------]
[Fig.4] Reset circuit
sv ~
'----v-------
FD resets softwarewise
[Fig.5] Reset circuit timings
Gate array
,
Inside , Outside
HIGH
ACTIVE
RSTN
PA
PB
LOW