Rear Panel; Digital Outputs; Digital Inputs; Word Clock Input / Output - DCS Vivaldi Upsampler User Manual

dCS Vivaldi Upsampler User Manual
R P
EAR ANEL
J K
L

Digital Outputs

All of the outputs consistent with the selected output mode are active at the same time.
The Vivaldi Upsampler generates 24-bit PCM data but it does not have facilities to reduce
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the word length to less than 24 bits. It will not give good results with older DACs (or other
equipment) that cannot process 24-bit data. ALL dCS converters will accept 24-bit PCM
data.
AES1 AES2
The and
or DSD in DoP format, or as a Dual AES pair at 88.2, 96, 176.4, 192, 352.8 or 384kS/s or DSD in DoP
format.
For Dual AES operation at 88.2, 96, 176.4 or 192kS/s or DSD, the
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menu page must be set to
data. If the output rate is 352.8 or 384, Dual AES mode is automatically selected.
2 SPDIF outputs are provided,
(L). These outputs carry SPDIF data for output rates at 32, 44.1, 48, 88.2, 96, 176.4 or 192kS/s or
DSD in DoP format, even if
352.8kS/s or 384kS/s.

Digital Inputs

The standard PCM inputs are
SPDIF3
connectors (N),
electrical inputs will accept up to 24-bit data at 32, 44.1, 48, 88.2, 96, 176.4 or 192kS/s or DSD in DoP
format. The Toslink input accepts data at up to 96kS/s.
SDIF
The interface will accept PCM data at sample rates up to 96kS/s. The interface consists of two
CH1
data inputs labelled
source is connected to the
correctly if the data sample rate changes but the Word Clock does not.

Word Clock Input / Output

Word Clock In
Either of the two
equipment or a master clock at 32, 44.1, 48, 88.2, 96, 176.4 or 192kHz. The clock frequency MUST be
an exact multiple of the data rate, otherwise the system will default to
Settings > Sync mode
word clock. The source MUST be locked to the same clock, otherwise the system will not be locked
and periodic clicks or other undesirable noises or dropouts will be heard on the outputs.
Filename: Vivaldi Upsampler Manual v1_0x.docx
M --N--
O Q
Figure 7 – Rear panel
outputs (J) can be used individually at 32, 44.1, 48, 88.2, 96, 176.4 or 192kS/s
Dual AES
SPDIF1
on an RCA connector (K) and
Dual AES mode is On. They are disabled when the Output mode is
AES
on a 3-way female XLR connector (M),
on a BNC connector (O) and
CH2
and (P). Operation in SDIF mode requires that a word clock from the
Word Clock In1
connectors (Q & R) will accept standard word clock from the source
menu page (see page 30) to lock the selected input to the selected external
--P-- U V W
R S T
On, otherwise both outputs will carry single AES
SPDIF4
on a Toslink connector (T). The
connector (Q). Note that the interface can fail to lock
Page 24
Software Issue 1.0x
November 2013
Y
X Z
Settings > Dual AES
SPDIF2
on a BNC connector
SPDIF1 SPDIF2
&
Audio sync. Use the
English version
on RCA