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The 16-bit memory address enters the board on the A
Bus and is used by the HRAM in the following ways:
1. The
Address Latches and decoders to determine if this
board should respond to the memory address.
2. The two most significant bits are used by the Cycle
Control and Strobe Generator to determine which of
the four rows of RAM chips should respond.
3. The least significant 14 bits are used by the RAM
array to determine the address inside the selected
RAM chips.
4. The least significant eight bits are used by the
Port
instruction is directed to the HRAM board.
5.2
ADDRESS MULTIPLEXER
The Address Multiplexer receives memory address bits
AO through A13 and sends these bits to the Memory
Array 7 bits at a time. Bits AO through A6 become the
row address for the RAM chips and bits A7 through A13
become the column address.
5.3
REFRESH LOGIC
The Refresh Logic supplies the RAM array with a 7-bit
address
determines which row of cells in the RAM chips is to
be refreshed on that particular refresh cycle. The
address automatically increments so that a different
address is presented on each refresh cycle.
The host system must generate at least 128 refresh
cycles in any 2 millisecond period. Because of this
requirement, the memory contents may be jeopardized by
a
single
milliseconds, or a series of short wait states.
The
instruction
provide two refresh cycles per byte moved.
5.4
PORT C0 DETECTOR
HRAM
four
most
significant
CO
Detector
on
each
memory
long
wait
Z80
initiates
read
bits
to
determine
refresh
state
on
one
refresh
cycle.
Block
USER/TECHNICAL MANUAL
are
used
by
when
an
output
cycle.
The
address
the
order
of
cycle
after
move
instructions
the
2
each
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