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10.
o
o
•
SERIES 7000 MEMORY CARD TIMING
Series 7000 cards are designed to communicate over the STD BUS backplane in any combination without
user timing considerations. The following information is provided to accommodate the useof pin compatible
memory chip variations which can be used in the Series 7000 memory cards.
Figure
lO-'
shows the functional blocks of the 7700 Memory cards. The delays contributed by these blocks are
added to the memory chip delays and access times to determine the AC characteristics of the card. The table
in Figure
,o~
gives maximum propagation delays for the memory card. For exact delays use the IC
manufacturer's data sheets and the appropriate schematics.
MEMlX·
ADDIIISI
BUI(HIGH,
ADDAESI
IIUS (LOW)
ADONSI
MIll OIl MIl AIItIA'I
DATA
DECODIIIS
IlUfnU
o---c
fl
a.-.
aw
I
1)
~
......
DATA
,
~
ADOIIEIII
_._.
DATA BUS
AOOIIESS
IlUfnIlI
'--<
-,
_TI
CONTIIOl
<>-¥-
~
~~l
?c
=D-
&,
(T"'"
MI_-'"
~
110-
~
WIIITI CIIICUlTIIY _lENT ONLY ON IIAM CAIIDI.
.,..
NOTU
F'cau.re
\0-1 Memory Card Functional Blocks
PROPAGATION DELAY
LOAD CONDITIONS
CIRCUIT
FROM
TO
. TpD MAX
CL
RL
MEMORY CHIP
ADDRESS
ADDRESS BUS
ENABLE
DECODERS
OR
OR
75 ns
15 pF
-
MEMEX'
READIWRITE
ENABLE
ADDRESS
ADDRESS
MEMORY CHIP
35 ns
160 pF
-
BUFFERS
BUS
ADDRESS
MEMORY CHIP
DATA
20 ns
45 pF
4.7Kn
DATA (OUT)
BUS
DATA
DATA
MEMORY CHIP
25 ns
80 pF
BUFFERS
BUS
DATA (IN)
-
READ WRITE
VALID OUTPUT
30 ns
CONTROL
ENABLE
READ
DECODER
ROM'
100 pF
4.7Kn
WRITE
OUTPUT
OR
70 ns
CONTROL
RD', WR',
WRM' (RAMs ONLY)
OR MEMRQ'
f
1C\0C't.
\C)-
a.
Generalized Maximum Delays For Memory Cards
For example, the 2114
RAM
chlpts speclfted Data Read a.cce~s~ ttJ1)e from
em
addre~s
change (AO-A9) is 450ns.
I n the 7701. th
is
increased by the add res's buffers (35ns}
and data buffers (20ns) to 505n5.
In thts case the decoding of A1Q-A15 and the
Data Bus buffer control are presumed to occur during the RAM data access' ttme,
13
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