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VBAT
C2085=REL1_05,REL1,REL1_SINGLE_SIM,REL3,REL5,REL7
C2086=REL6,REL2,REL4
VBATT
J2081
GND
+
C2082
C2084
C2085
C2086
C2083
10p
100n
47p
56p
150u_10V
J2082
not_assembled
L2055
X2000
F2051
28R/100MHz
2.0A
K
R2212
R2050
C2058
C2059
27p
470n
A
R2213
R2214
VBAT_BB
C2221
R2202
1V8
10u
10k
V2200
V2201
R2204
220k
2
1V8
SLOWAD(6:0)
X2080
R3005
150k
R2083
J2080
BSI
10k
-t
C2081
R2080
R2084
R2082
27p
18V/60V
47k
120k
VBAT
R2208
V2204
E2201
SENSEN
0R15
R2210
R2220
C2208
27k
1k5
470R
1n0
3
SENSEP
R2211
5
CSB
12k
3k3
6
2
4
V2205
CS
1
V2205
VDDCHG
1k5
VSHNT
VCHG
C2218
C2220
C2219
C2217
82p
82p
82p
82p
VBAT
R2200
0R15
R2201
10k
V2200
R2203
82k
VCORE
VAUX
1V8
L2204
3u3H
C2204
C2206
C3023
C2209
C2205
27p
22U
100n
0u47
220n
VBAT_BB
C2215
C2216
C2207
2u2
2u2
10u
C3016
33n
C3022
C3001
C2213
C2203
4n7
100n
1u
100n
D3100
F6
CLKOUT2
N12
M0
R11
M2
G7
B3
EN
CIF_PD
A6
J3003
D5
D1
CIF_D0
B6
E5
D2
CIF_D1
C5
D4
D3
CIF_D2
A7
D3
D4
CIF_D3
B7
D2
D5
CIF_D4
C6
D1
D6
CIF_D5
C7
E1
D7
CIF_D6
E8
C3
D8
CIF_D7
G6
J3002
E3
CLK
CIF_PCLK
F7
J3005
C2
CIF_HSYNC
H-SYNC
E7
J3006
B2
V-SYNC
CIF_VSYNC
L6
SENSEN
M6
SENSEP
R6
CSB
M7
CS
T4
VDDCHG
K6
VSHNT
T5
VCHG
A3,B1,E2,E4=GND
1V8
1V8
R3022
R3023
k37
4k7
P9
ANAMON
A5
1
I2C_SDA
0
B5
I2C_SCL
M8
VSIM
C2211
R3014
100n
4k7
G3
CC_IO
G2
CC_CLK
G4
CC_RST
TEMP4
H8
DUAL_SIM_INT
G8
USIF2_TXD_MTSR
VDDCORE
K8
VCORE
P8
VAUX
J10
CLK32K
VDD1V81
R7
SD1SW
J3007
A4
CLKOUT0
1V8
VBAT_BB
C2755
C2754
100n
2u2
N8
VBAT_PMU
P16
VBATSP
P7
VDD_SD1
K12
DMINUS
K11
DPLUS
R15
M9
CP2
VUSB
T15
CP1
N11
VDDFMR
A2
C2210
R16
VDDNEG
100n
T10
A1
VREF
P10
VPMU
B1
G9,J10,K7,R5,P14,T6=1V8
A1,A16,C15,E12,F8,F12,F13,F14,F15,G12,H9,J9,
L8,L14,M10,M11,P11,P14,P15,R8,T7,T9,T16=GND
R1401
33R
N3000
1V8
R1402
C4
Class_Sel
4k7
C1
VL
C5
VL
B4
Sync_Sel
C3017
C3018
10n
0u47
VAUX
B5
VDD
C3019
J1401
10n
0
J1402
1
J1403
R3020
A4
STRB-
100R
A5
STRB+
R3019
A1
D-
100R
A2
D+
I2C(1:0)
D2750
4
SLOWAD(6:0)
BSI
1
24
SDA
0
23
SCK
2
RESETX
11
DUAL_SIM
C2
VSIM1
13
J2751
SIM_IO
A3
IO1
14
J2752
SIM_CLK
B3
CLK1
12
J2750
SIM_RST
C3
RST1
18
IO
17
CLK
16
RST
1
IRQ
C2752
1u
8
C2
VSIM2
22
6
J2754
A3
CLKIN
IO2
5
J2755
B3
CLK2
7
J2753
C3
RST2
3
VSIM2_DET
21
VDDIO
9
VDDBAT
10,19,20,25=GND
R2755
C2753
18V/30V
1u
X2052
VBUS
1
VBUS
D-
2
D+
3
ID
R2065
C2054
C2052
18V/30V
27p
4u7
V2050
B2
X2-02 RM-694 | Board: 3kp_40c | v1.0 | 01.12.2011
CIF_CMT(13:0)
VAUX
H1400
1
L1400
2
XSHUTDOWN
3
600R/100MHz
EXTCLK
4
CCISCL
5
C1404
C1401
C1403
6
CCISDA
1V8
220n
100n
27p
7
CCPCLK_N
8
CCPCLK_P
9
10
CCPDATA_N
11
CCPDATA_P
12
C1400
C1402
C1405
GND
100n
27p
10u
R2750
X2750
Side
A2
SIM_CON0_IO
5
R1
CLK
B1
SIM_CON0_CLK
1
R2
C1
SIM_CON0_RST
2
R3
VSIM1_CON0
3
C2750
7=GND
100n
R2751
X2752
Side
A2
SIM_CON1_IO
6
R1
C3
CLK B1
SIM_CON1_CLK
3
R2
C7
C1
SIM_CON1_RST
2
R3
C6
VSIM2_CON1
1
C5
VSIM2_DET
8
SW1
9
SW2
C2756
5,10,11,12,13,14,15,16,
100n
17,18,19,20,21=GND
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