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3 7 63 1515 0
6-7 Progressive Convert DAC : PM0026A (X25, IC601) DV-5050M/DVF-J6050 only
• Port Function
Port No.
Port Name
1
VDD3
2~8
VIB9~VIB3
9~11
GND
12~14
VIB2~VIB0
15,16
DOS1, DOS0
17~19
TEST2~TEST1
20
VDD3
21
VDD2
22
AGND
23
DAO Y
24
AVDD2
25
DAO B
26
AGND
27
DAO R
28
AVDD2
29
VREF
30
FSADJ
31
AVDD2
32
VG
33
AGND
34
CLMP
35
SPR7/V09
36
GND
TE
L 13942296513
SPR4/V06~
37~39
SPR6/V08
40,41
VDD3
42
GND
SPR1/V03~
43~45
SPR3/V05
46
SPR0/V02
47
VO1
48
VO0
49
VDD3
50~52
GND
53
RMA5
54~56
RMA4~RMA2
57
GND
58
CLK
59
SRP
60
VDD3
61
VDD2
62
CSB
63
SDATA
64
SCLK
65
RMA1
66
RMA0
www
67
CKPOL
68
VIA9
69~76
VIA8~VIA1
.
77
VIA0
78
NVS
79
NHS
80
VDD3
DV-5050M/5900M/DVF-J6050/J6050-G
CIRCUIT DESCRIPTION
I/O
-
Positive supply voltage (+3.3V) for pad ring.
I
Connected to digital ground.
-
Digital ground for core.
I
Connected to digital ground.
I
Connected to digital ground.
I
Connected to digital ground.
-
Positive supply voltage (+3.3V) for pad ring.
-
Digital positive supply voltage (+2.5V) for core.
-
Analog ground for D/A converter.
O
Y analog output.
-
Positive supply voltage (+2.5V) for D/A converter.
O
Cb analog output.
-
Analog ground for D/A converter.
O
Cr analog output.
-
Positive supply voltage (+2.5V) for D/A converter.
I
Reference voltage input for 3DACs.
I/O
Current source for full scale adjustment of 3DACs.
-
Positive supply voltage (+2.5V) for D/A converter.
O
Compensation pin for gate voltage of DAC current cells.
-
Analog ground for D/A converter.
O
Unused.
O
Unused.
-
Digital ground for core.
Multi-purpose parallel output converted from serial data through MPU interface / pixel
O
data output.
-
Positive supply voltage (+3.3V) for pad ring.
-
Digital ground for core.
Multi-purpose parallel output converted from serial data through MPU interface / pixel
O
data output.
Multi-purpose parallel output converted from serial data through MPU interface (LSB) /
O
pixel data output.
O
Pixel data output.
O
Pixel data output (LSB).
-
Positive supply voltage (+3.3V) for pad ring.
-
Digital ground for core.
I
Address input for monitoring internal register (MSB).
I
Address input for monitoring internal register.
-
Digital ground for core.
I
System clock input (27MHz).
I
System reset input (negative).
-
Positive supply voltage (+3.3V) for pad ring.
-
Digital positive supply voltage (+2.5V) for core.
I
Chip select input of MPU serial interface.
I
Data input of MPU serial interface.
I
Clock input of MPU serial interface.
I
Address input for monitoring internal register.
I
Address input for monitoring internal register (LSB).
-
Internal clock. polarity control input.
x
ao
u163
y
I
Pixel port A input (MSB).
I
Pixel port A input.
i
I
Pixel port A input (LSB).
I/O
Active low vertical sync.
I/O
Active low horizontal sync.
-
Positive supply voltage (+3.3V) for pad ring.
2 9
8
Function
Q Q
3
6 7
1 3
1 5
co
.
9 4
2 8
0 5
8
2 9
9 4
2 8
m
9 9
9 9
23
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