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QQ
3 7 63 1515 0
Port No.
120,130
121
122
123
124
125,135
126
127
128
129
131
132
133
134
136
137
138
139
140,141
142
143
144
145
147~150,152~155
158,159,161,162,
TE
L 13942296513
164,165,167,168,
170,171,173,175,
177,178,180181
183
185
187
189
190
192
193
195
196
198
199
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DV-5050M/5900M/DVF-J6050/J6050-G
CIRCUIT DESCRIPTION
Port Name
I/O
AVDD(1,0)
-
Analog supply voltage (+3.3V) for DAC.
VREFG
I
DAC reference voltage input for Cb signal.
IREFG
I
DAC bias current setting port for Cb signal.
COMPG
I
Capacitance connection for DAC (Cb signal) stabilization.
VGBOUT
O
Cb signal output for DAC.(Unused)
AVSS(0,1)
-
Analog ground for DAC.
VREFC
I
DAC reference voltage input for Cr, C signal.
IREFC
I
DAC bias current setting port for Cr, C signal.
COMPC
I
Capacitance connection for DAC (Cr, C signal) stabilization.
VCOUT
O
Unused.
VREFY
I
DAC reference voltage input for Y signal.
IREFY
I
DAC bias current setting port for Y signal.
COMPY
I
Capacitance connection for DAC (Y signal) stabilization.
VYOUT
O
Y signal output for DAC.
NC
-
Unused.
ACKIO
-
Connected to digital ground.
MODE121
I
Connected to digital ground.
PLLTEST
I
Connected to digital ground.
TESTSEL1,0
-
Test mode terminal. L : Fixed
DCTEST
-
DC test mode terminal.
XYSYNCO
I/O
Vertical synchronizing signal input/output.
XHSYNCO
I/O
Horizontal synchronizing signal input/output.
VCLK
O
Clock output for digital video data output.
VD0~VD7
O
Digital video data output (0~7)
MDQ0~MDQ15
I/O
SDRAM data bus (0~15).
MCKI
I
Clock input from SDRAM.
MCK
O
Clock output to SDRAM.
DQMLE
O
Lower bite data, mask signal of expander SDRAM.
DQMLM
O
Lower bite data, mask signal of main SDRAM.
DQMUE
O
Upper bite data, mask signal of expander SDRAM.
DQMUM
O
Upper bite data, mask signal of main SDRAM.
XWE
O
Write enable signal of SDRAM.
XCAS
O
CAS signal of SDRAM.
XRAS
O
RAS signal of SDRAM.
XCSE
O
Chip select signal of expander SDARM.
XCSM
O
Chip select signal of main SDARM.
x
ao
y
i
8
Q Q
3
6 7
1 3
u163
.
2 9
9 4
2 8
Function
1 5
0 5
8
2 9
9 4
m
co
9 9
2 8
9 9
15
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