Yamaha DSP-A5 Service Manual page 28

DSP-A5
IC5 : IS61C1024-20J (1M SRAM)
131072-word x 8-bit High Speed Static RAM
NC 1
2
A3
3
A4
A5 4
5
A6
6
A7
A8 7
8
A9
9
A10
A11 10
11
A12
12
A13
D1 13
14
D2
15
D3
GND 16
NOTE)
A0-A16:
D1-D8:
/CE1,CE2: Chip enable input 1,2
/OE:
/WE:
IC7 : AK4324-VF-E2 (DAC)
1-bit D/A Converter
1
DVSS
2
DVDD
CKS 3
4
MCLK
5
/PD
BICK 6
7
SDATA
LRCK 8
SMUTE 9
10
DFS
DEM0 11
DEM1 12
Pin Pin
I/O
No. Name
1 DVSS Ground (digital)
2 DVDD Power supply (digital)
3 CKS I Master clock (MCLK) select input (Fixed L)
Normal speed (L:256fs, H:384fs)
High speed (L:128fs, H:192fs)
4 MCLK I 256fs bit clock input from DIR5
5 /PD I Power-down and reset, initial clear input from
AC3D2av (L:Reset)
6 BICK I 64fs bit clock input from DIR5
7 SDATA I Serial data input from AC3D2av
8 LRCK I 1fs word clock input from DIR5
9 SMUTE I Soft mute detect input (H:Soft mute, L:off)
10 DFS I Double speed sampling mode select input from
DIR5 (L:Normal speed, H:High speed)
27
32 VCC
31
A2
30
CE2 A0-A16
29 /WE
28
A1
27
A0
26 A16
D1-D8
TOP VIEW
25
A15
24
/OE
23 A14
22
/CE1
21
D8
20 D7
19
D6
18
D5
17 D4
Address input
Data input/output
Output enable input
Write enable input
24 DZFL
23 DZFR
22 AVDD
21 VREF
20 AVSS
19 AOUTL+
TOP VIEW
18 AOUTL-
AOUTR+
17
16 AOUTR-
15
DIF2
14 DIF1
13 DIF0
Function
27,28
31,
2-12, DECODER
23,25
26
I/O DATA
13-15,
17-21
CONTROL
/CE1
22
CE2
30
CONTROL
CIRCUIT
/WE
29
/OE
24
Mode /WE /CE1
Not Selected X H
(Power-down) X X
Output Disabled
H L
Read H L
Write L L
NOTE) H: High Level L: Low level
DIF0 DIF1 DIF2 DEM0
13 14 15 11
LRCK
8
SERIAL INPUT DE-EMPHASIS
BICK
6
INTERFACE
SDATA
7
8x
/PD
5
INTERPOLATOR MODULATOR
SMUTE
9
8x
INTERPOLATOR MODULATOR
DFS
10
CLOCK
DIVIDER
4 3
MCLK CKS DVDD
Pin Pin
I/O
No. Name
11 DEM0
12 DEM1
13 DIF0
14 DIF1
15 DIF2
16 AOUTR- O Rch negative analog output
17 AOUTR+ O Rch positive analog output
18 AOUTL- O Lch negative analog output
19 AOUTL+ O Lch positive analog output
20 AVSS
21 VREF
22 AVDD
23 DZFR O Rch zero input detect output
24 DZFL O Lch zero input detect output
131072-word x 8-bit
MEMORY ARRAY
(512-row x 2048-column)
COLUMN I/O
/CE2 /OE Data I/O Power
X X High impedance Standby
High impedance
L X On
High impedance On
H H
H L Output On
Input On
H X
X: Don't care
DEM1 AVDD AVSS
12 22 20
24
CONTROL
∆∑ 19
SCF
18
∆∑
17
SCF
16
23
2 1 21
DVSS VREF
Function
I De-emphasis frequency select input 0 (Fixed H)
I De-emphasis frequency select input 1 (Fixed L)
I Digital input format input 0 (Fixed L)
I Digital input format input 1 (Fixed H)
I Digital input format input 2 (Fixed L)
Ground (analog)
I Reference voltage input
Power supply (analog)
32 VCC
16 GND
DZFL
AOUTL+
AOUTL-
AOUTR+
AOUTR-
DZFR