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VD_CORE
U401H
VDDC: 1.0V, core power
R403
4.7K 1/16W
16,17
FRA11
R404
0R05 OHM
R406
4.7K 1/16W
16,17
F_WE
R407
0R05 OHM
R409
4.7K 1/16W
16,17
F_OE
R410
0R05 OHM
R412
4.7K 1/16W
16,17
FRA8
R413
NC 0R05 OHM
R415
4.7K 1/16W
16,17
FRA14
R416
NC 0R05 OHM
R418
4.7K 1/16W
16,17
FRA13
R419
0R05 OHM
R421
4.7K 1/16W
16
FRA15
R422
0R05 OHM
R426
4.7K 1/16W
16,17
FRA10
R427
0R05 OHM
R431
4.7K 1/16W
16,17
FRA6
R432
0R05 OHM
R436
4.7K 1/16W
16,17
FRA7
R437
0R05 OHM
R441
4.7K 1/16W
16,17
FRA12
R442
NC 0R05 OHM
R444
4.7K 1/16W
16,17
FRA0
R445
0R05 OHM
R447
4.7K 1/16W
16,17
FRA5
R448
0R05 OHM
V_3.3
3.3VSB
VDDF: for
VDDF_ST B: for
3 .3V digit al IO
3.3V ST B IO
ASXL
27x27
(3/8)
POWER/GROUND
Boot from SPI (System Config NAND+SPI)
V_3.3
No
PIN
Configure Pin
R405
NC 4.7K 1/16W
1
FRA11
MIPS Boot ROM width selection
R408
NC 4.7K 1/16W
Internal E2PROM or EFUSS burning mode selection
2
F_WE
(Option 1 only used in Chip production)
R411
NC 4.7K 1/16W
3
F_OE
EJTAG Mode Selection
R414
4.7K 1/16W
4
FRA8
Seclet internal 8051 bus or Slave I2C for debug
5
FRA14
Internal 8051 bus Master/Slave selection
R417
4.7K 1/16W
6
FRA13
OneNand Flash sync mode clock enable
R420
NC 4.7K 1/16W
7
FRA15
Boot from SPI or Parallel Flash
R423
NC 4.7K 1/16W
8
FRA10
NAND boot enable
R428
NC 4.7K 1/16W
9
FRA_[7:6]
NAND TYPE
R433
NC 4.7K 1/16W
R438
NC 4.7K 1/16W
10
FRA12
CPU Little Endian Mode enable
11
FRA0
Control Core MIPS Clock Switch
R443
4.7K 1/16W
12
FRA5
Control CPU_CLK Clock Switch
R446
NC 4.7K 1/16W
MASTSEL
Lexru Bus Master Select
R449
NC 4.7K 1/16W
STB_EN
StandBy Mode Enable
V_1.5
V_3.3
C446
4.7UF 10V
VDDM : 1.5V, m em o ry I/O power
V_1.5
C455
10UF
SCALER TSXLFF-B1AFFFH BGA 27*27
VD_CORE
C477
10UF
10N 50V
10N 50V
C487
Description & Setting(* as default setting)
0 : 8bit
1 : 16bit(*)
0 : normal function(*)
1 : burn code for eeprom
0 : non-daisy chain mode(*) 1 : daisy chain mode
0 : Disable Slave I2C/Enable 8051
1 : Enable Slave I2C/Disable 8051(*)
0 : Slave 8051
1 : Master 8051 (*)
0 : ASYNC mode
1 : SYNC mode(*)
0 : SPI Enabled 1 : Parrallel FLASH Enabled(*)
0 : Disable boot from Nand(*)
1 : Enable boot from Nand
00 : address mapping mode 1(*)
01 : address mapping mode 2
10 : address mapping mode 3
11 : address mapping mode 4
0 : little endian 1 : big endian(*)
0 : Normal(*) 1 : Internal Switch Inverted
0 : Normal(*) 1 : Internal Switch Inverted
0 : Internal 8051(*) 1 : External 8051(ATE mode)
0 : disable 1 : enable(*)
T P V ( Top
絬 隔 瓜 絪 腹
Key Component
07: SXL power 3
Friday , April 15, 2011
Date
35
4.7UF 10V
100N 16V
100N 16V
100N 16V
100N 16V
100N 16V
C447
C448
C449
C450
C451
C452
100N 16V
100N 16V
100N 16V
10UF
10UF
10UF
10UF
100N 16V
100N 16V
C456
C457
C458
C459
C460
C475
C462
C463
C464
10UF
10UF
10UF
100N 16V
100N 16V
100N 16V
100N 16V
100N 16V
C478
C479
C480
C481
C482
C483
C484
C485
10N 50V
10N 50V
10N 50V
10N 50V
10N 50V
10N 50V
10N 50V
C488
C489
C490
C491
C492
C493
C494
C495
Work Mode
Normal Mode
EJTAG Mode
Scan Mode
Simulation Mode(ATE)
17
SX_TESTMOD
17
SX_TESTCON
16
MASTSEL
17
STB_EN
Victory
Electronics
Co . ,
Ltd. )
OEM MODEL
TPV MODEL
PCB NAME
Sheet
7
of
25
3.3VSB
C453
C454
10UF
10N 50V
10N 50V
10N 50V
100N 16V
10N 50V
10N 50V
C465
C466
C467
C468
C476
100N 16V
C486
10N 50V
10N 50V
C496
C497
TESTMOD
TESTCON
0
0
0
1
1
0
1
1
3.3VSB
R424
0R05 OHM
R425
NC 4.7K 1/16W
R430
R429
4.7K 1/16W
0R05 1/10W
R434
0R05 OHM
R435
NC 4.7K 1/16W
R439
R440
4.7K 1/16W
NC 0R05 OHM
Size
A3
Rev
B
称爹
<称爹>
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