Clarion DRZ9255 Service Manual page 10

051-6708-90 AK4121VF Asynchronous Sample Rate Converter
Terminal Description
pin 1: FILT : O : PLL filter output.
pin 2: A VSS : - : Negative voltage supply for analog section.
pin 3: PDN : IN : Power down & reset signal input.
pin 4: S MUTE : IN : The soft muting command input.
pin 5: DEM 0 : IN : De-emphasis Frequency Selection.
pin 6: DEM 1 : IN : De-emphasis Frequency Selection.
pin 7: I LR CK : IN : Left/Right clock input for the input signal.
pin 8: I BI CK : IN : Bit clock input for the input signal.
pin 9: SDT I : IN : The serial data input.
pin 10: I DIF 0 : IN : Input data format select.
pin 11: I DIF 1 : IN : Input data format select.
pin 12: I DIF 2 : IN : Input data format select.
pin 13: C MODE 0 : IN : The clock mode select.
pin 14: C MODE 1 : IN : The clock mode select.
pin 15: C MODE 2 : IN : The clock mode select.
pin 16: O DIF 0 : IN : Output data format select.
pin 17: O DIF 1 : IN : Output data format select.
pin 18: SDT O : O : The audio serial data output.
pin 19: O BI CK :I/O: Bit clock input/output for the output signal.
pin 20: O LR CK :I/O: Left/Right clock input/output for the output
signal.
pin 21: MASTER CLK : IN : Master clock input.
pin 22: T VDD : - : Positive voltage supply for output-buffer.
pin 23: D VSS : - : Digital ground.
pin 24: VDD : - : Positive voltage supply.
Table 1. Master/Slave control
Cmode 2 Cmode 1 Cmode 0
(pin 15) (pin 14) (pin 13)
L L L 256fso(fso to 96kHz)
L L H 384fso(fso to 96kHz)
L H L 512fso(fso to 48kHz)
L H H 768fso(fso to 48kHz)
H L L
H H H
Table 2. Input Audio data Formats
I DIF 2 I DIF 1 I DIF 0
(pin 12) (pin 11) (pin 10)
L L L
L L H
L H L
L H H 20/16bit I2C compat.
H L L
Table 3. Output Audio data Formats
O DIF 1 O DIF 0 SDT O format
(pin 17) (pin 16) (pin 18)
L L 16bit LSB Justified
L H 20bit LSB Justified
H L 20/16bit MSB Justif.
H H 20/16bit I2C compat.
Table 4. De-emphasis filter control
DEM 1 (pin 6) DEM 0 (pin 5)
L L
L H
H L
L H
DRZ9255
HX-D2
Master CLK Master/Slave
(pin 21) (Output port)
Master
Master
Master
Master
Connect to DVSS Slave
Connect to DVSS Master(bypass mode)
SDT I format I BI CK (slave)
(pin 9) (pin 8)
16bit LSB Justified 32 or less
20bit LSB Justified 40 or less
20bit MSB Justified 40 or less
32/40fs or less
24bit LSB Justified 48 or less
O BI CK O BI CK
(Slave) (Master)
64fs
64fs
32/40fs or less
32/40fs or less
De-emphasis filter
44.1kHz
off
48.0kHz
32.0kHz
051-6071-08 BA5825FP-E2
Truth Table
MUTE
(pin 9)
H
H
L
L
051-5036-90 PGA2310UA
ZCEN
CS_
S Data I
D VDD
D GND
S CLK
S Data O
64fs
Mute In
64fs
64fs
Terminal Description
64fs
pin 1: ZCEN
pin 2: CS IN
pin 3: S DATA IN
pin 4: D VDD
pin 5: D GND
pin 6: S CLK
pin 7: S DATA OUT
pin 8: MUTE IN
pin 9: R A IN
pin 10: R A GND
pin 11: R A OUT
pin 12: A V+
pin 13: A V-
pin 14: L A OUT
pin 15: L A GND
pin 16: L A IN
- 10 -
2.4V
Level
Shift
Level
Shift
2.4V
CNT CH1,2,3
(pin 21) output
H MUTE OFF
L MUTE OFF
H MUTE ON
L MUTE ON
Stereo Volume Controller
1
2
3
Logic
Control
4
5
6
7
8
: IN : Zero Cross Enable signal input.
: IN : The chip select command input.
: IN : The serial data input.
: - : Positive voltage supply for digital section.
: - : Digital ground.
: IN : The serial clock input.
: O : The serial data output.
: IN : Mute command input.
: IN : Right channel audio signal input.
: - : Right channel audio signal ground.
: O : Right channel audio signal output.
: - : Positive voltage supply for analog section.
: - : Negative voltage supply for analog section.
: O : Left channel audio signal output.
: - : Left channel audio signal ground.
: IN : Left channel audio signal input.
Quad Motor Drivers
Level
Shift
Level
Shift
CH4
output
LD ON
SL ON
LD ON
MUTE ON
16 L IN
15 L A GND
14 L OUT
13 A V-
12 A V+
11 R OUT
10 R A GND
9 R IN