Memory - LG KP500 Service Manual
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3.6 Memory
2Gbit NAND & 1Gbit DDRSDRAM employed on KF500 with 8 & 16 bit parallel data bus thru ADD(0) ~
ADD(29). The 1Gbit Nand Flash memory with DDRAM stacked device family offers multiple high-
performance solutions.
D A
( D
6 1
2 :
) 9
D A
D
1 (
) 6
D4
A0
D A
D
1 (
) 7
E4
A1
D A
D
1 (
) 8
F4
A2
D A
D
1 (
) 9
G4
A3
D A
D
2 (
) 0
G8
A4
D A
D
2 (
) 1
F8
A5
D A
D
2 (
) 2
E8
A6
D A
D
2 (
) 3
D8
A7
D A
D
2 (
) 4
D9
A8
D A
D
2 (
) 5
G7
A9
D A
D
2 (
) 6
G5
A10
D A
D
2 (
) 7
F7
A11
D A
D
2 (
) 8
E7
A12
D A
D
2 (
) 9
E9
D A
D
0 (
1 :
) 5
A13
D A
D
) 0 (
L4
DQ0
D A
D
) 1 (
M4
DQ1
D A
D
) 2 (
N4
DQ2
D A
D
) 3 (
L5
DQ3
D A
D
) 4 (
M5
DQ4
D A
D
) 5 (
N5
DQ5
D A
D
) 6 (
M6
DQ6
D A
D
) 7 (
N6
DQ7
D
) 8 (
D A
M7
DQ8
D A
D
) 9 (
N7
DQ9
D A
D
1 (
) 0
L8
DQ10
D A
D
1 (
) 1
M8
DQ11
D A
D
1 (
) 2
N8
DQ12
D A
D
1 (
) 3
L9
DQ13
D A
D
1 (
) 4
M9
DQ14
D A
D
1 (
) 5
N9
DQ15
K6
B _
0 C
LDQM
K7
B _
1 C
UDQM
L6
D L
Q
S
LDQS
L7
U
D
Q
S
UDQS
C6
D S
L C
I K
_CLK
C7
D S
C
K L
O
CLK
D7
C
E K
CKE
TP203
E5
B
0 A
BA0
TP204
F5
B
1 A
BA1
F6
R _
S A
_RAS
E6
C _
S A
_CAS
D6
_
W
R
_WED
TP205
D5
_
A R
_ M
S C
_CS
Figure 9 Flash memory & DDR RAM MCP circuit diagram
Copyright © 2008 LG Electronics. Inc. All right reserved.
Only for training and service purposes
U201
H8BCS0SI0MAP_56M
EUSY0347503
- 41 -
3. TECHNICAL BRIEF
D
A
A T
0 (
1 :
) 5
D
A
A T
) 0 (
P10
I_O0
D
A
A T
) 1 (
N10
I_O1
D
A
A T
) 2 (
M10
I_O2
D
A
A T
) 3 (
L10
I_O3
D
A
A T
) 4 (
F10
I_O4
D
A
A T
) 5 (
E10
I_O5
D
A
A T
) 6 (
D10
I_O6
D
A
A T
) 7 (
C10
I_O7
D
A
A T
) 8 (
N11
I_O8
D
A
A T
) 9 (
M11
I_O9
D
A
A T
1 (
) 0
L11
I_O10
D
A
A T
1 (
) 1
K11
I_O11
D
A
A T
1 (
) 2
G11
I_O12
D
A
A T
1 (
) 3
F11
I_O13
D
A
A T
1 (
) 4
E11
I_O14
D
A
A T
1 (
) 5
D11
I_O15
TP200
G3
_CE
N _
N A
_ D
S C
TP201
M3
_WEN
_
W
R
TP202
F3
_RE
R _
D
L3
ALE
D A
D
1 (
) 6
K3
CLE
D A
D
1 (
) 7
E3
R__B
N3
_WP
H2
VCCN1
SD_1V8
C5
VSS1
C9
VSS2
G2
VSS3
H10
VSS4
P7
VSS5
SD_1V8
P9
VSS6
P5
VSSQ
C4
VDD1
C8
VDD2
P6
VDD3
P4
VDDQ1
P8
VDDQ2
LGE Internal Use Only
SD_1V8
C F
D
P
_
W
P
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