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more about Sharp
PC-1500
at http:f/www.PC-1500.info
5
PERIPHERAL
STATUS
INTERRUPT
(PSI)
:
This bit is se
t
high by a
high·t<>-low voltage
transition
of
Term.
37 (PSI). The INTERRUPT
out.
put (Term. 13) is also asserted
(
INT
=
low)
when
this bit is
set.
6 T
RANSMITTER
SHIFT
REGISTER EMPTY
(TSRE):
When set high
, this
bit
indicates
that the Transmitter
Shift
Register
has
completed
serial
trans·
mission of
a
full
character including stop
bit(s).
It
remains
sci
until the
start or transmission
o
f
rhe
next
character.
7
TRANSMITTER
HOLDING
REGISTER
EMPTY
(THRE):
When
set
high,
this bi
t
indicates
that the
Transmi tter Hol ding Register has transferred its
contents
to the Transmitter Sh ift
Register
and may be reloaded
with
a new character. Setting this
bit also sets the
THRE
output
(Term. 22) low and
causes
an
INTERRUPT
(INT=
low),
if T
R
is
high.
4. Peripheral
Int
erface
14
In
addition
to
serial
data in and
o ut,
four
signals arc provided for communication with
a
peripheral.
n ie
REQUEST TO SET
NT
(
RTS) output
signal alerts the
peripheral
to
gel
ready
10
receive data.
The
CLEAR TO SEND
(CTS)
input signal
is
the
response,
signalling
that
the peripheral
is
ready. The
EXTERNAL
STATUS (ES) input latches a peripheral Slatus
level, and
the PERIPH ERAL STATUS
IN TERRUPT
(PSI) input
senSC$
a
status
edge (high·lo·low) and
also
generates an
interrupt
.
Fo
r
example, the modern
DATA
CA
RRIER DETECT line
could
be
connected
to the
l'sfinpul
on
the
UART in order to
signal the
microprocessor that
transmission failed because
of
loss of the
carrier
on
the
communications
line. The
PSI and
ES
bits
arc stored
in
the Sta
tus Register (See F ig.
4
).
~
:
-1oc
•
so1-----i
:
S
fAAT Bil
PAHnY
I
srOP
err
t
A(AO••
~~---t------~-------------T-'---
--t
I
TT~
TPS
_ _ _
__,
OE•
' - - - - -
-- - -
-- - -
--
- - -
_.)
;
!--• COL
:
ICP~
:----:
··· ~-----------------------.;,....;_
1'CPt
,.....-.
Ft;I
-
- ----------------
---=--'--
Fig.
5
- MODE I receiver timing
diagram.
'
I
I'
A START BIT
OCCURS
AT
A
TIME LESS
THAN Toe DE FO
RE A fllGH·'f().LOW
T RANSITION
O
F
'Jll
E
CLOCK.
T
HE START BIT
MAY NOT
RE
R
ECOG
NIZED UNTIL
T
HE
NEXT
JllGll·TO·
l
.
.
O
W
TRANSITION
OF
T HE
CLOCK,
T HE START
arr
MAY IHO CO
MPLETELY
ASYNCHRO
NOUS WIT.H
TllECLOCK.
"
RE
AD
JS
THE
OVERLAP OF
CSI
,
CS3.
R
D/WR
•
1
AND
CS2
•
O.
II'
A PE NDING DA HAS
N
OT BEEN CLEA
RE
D
BY A
REA
D O
F THE RECEI
VER HOLDING
REGIST
E
R BY
THE
T
IME
A
NEW
WOR
D
I
S LOADED
t
NTO
TllE RECEIVER
llOLDINC
REGISTER
,
Til
£
0F.
SIGNAL WI LL
COME
T
RUE.
t
0£ AND
P£
SHARE TERMINAL JS
AND
ARE ALSO AVAILABLE AS 1'1'0 SEPARATE BITS JN TIIE
STATUS
REGISTER.
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