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6. LSI Discription
CDP1854A, COP1854AC
Types
1. Initialization
and
Controls
In
this mode
.
the CDPJ854A is configured to receive commands and send stal\Js via
the
micro-
processor dat.a
bus.
The
register connected
to the
transmitter bus or the receiver bus
is determined
by
the
RD/WR
and
RSEL
inputs as
follows:
TAB
LE
1-Register
Se•,ction
:;um•nary
RSEL
RD{WR
Function
Low
LO\V
Load
Transmitter Holding Register
from
Transmitter Bus
LO\\'
High
Read
Receiver
Hod Ung Register from
Receiver
Bus
High
Low
Load Control Register from
Tranm1iltcr
Hus
High
Low
Read Status Register from Receiver
Bus
In this mode
the
CDPJ854A
is
compatible with a
bidirectional bus system.
The receiver
and trans·
rnitter
buses
are
connected
to the
bus.
The CLEAR input
is
pulsed, resetting
the
Control, Status,
and
Receiver Holding
Registers
and setting S.ERIAL DATA OUT(SDO)
high.
The Control
Register
is loaded fronn the
Trans111itter Bus in
order to deter1nine
the
o
per3ting
configuration for tlu?
UART.
Data is
transferred
from the
Transmitter
Bus inputs to the Control
Register during TPB
when the
UART is
selected (CS I
·
CS2
· CS3·1
)
and the
Control
Register
is designated (RSEL
=
H.
RD/WR
=
L).
Titc CDPI 854A
also
has
a Status Register wltich
can
be
read
onto the Receiver Bus
(R
BUS O-
R BUS
7)
in order
to
determine
the status of
the
UART. Some of
these status
bits are also available
at
separate te rminals as
indicated in
Fig.
7.
2. Transmitter
Operation
Before beginning
to
traMmit.
the TBANSMIT REQUEST (TR) bit in the Control
Register
(see
bit
assignment,
Fig.
3) is
set.
Loading
the Control
Register
with TR
=
I
(bit
7
=
ihig)1) inhibits changing
the
other
con
trol
bits. Therefore
two loads
arc
required
:
one to format the
UART,
the second to
set
TR.
1~1ien
TR
has been
set,
a
TRANSMITTER
HOLDING REGISTER EMPTY (THRE)
inter-
rupt
will
occur. signalling
the
micropr<icessor
that
the
Transmitter
Holding Register
is
empty and
may be
loaded.
Setting TR
also
causes
asscrhon of
a
low-level
on the REQUEST TO
SENT
(RTS)
output
to the
peripheral.
It
is
not
necessary to set TR for
proper
operation for
the
UART.
If de-
sired,
it
can
be used to enable THRE
intcrr~1pts
and
to
generate
the RTS
s]gnaL
The
Transmitter
Holding Register
is
loaded from the
bus
by TPB during
execution
of an output
instruction.
The
CDPI
854A
is
selected
by
CS!
•
CS2
•
CS3 -
I, and
the
Holding Register
is selected
by
RSEL
=
L
and
RD/WR
=
L. When the
CLEAR
TO SEND (CTS) input, which can be connected to a
peripheral
device
output,
goes
low,
the Transmitter
Shift
Register
will
be
loaded
from the
Transmit·
ter
Holding
Register
and
data transmission will
begin.
If CTS is
always
low, the
Transmitter
Shift
Register will be loaded
on t.he first high-to.low edge
of
the
clock which occurs at
least
1/2
clock
period
after 'the trailing edge of
TPll
and transmis.•ion of a start
bit
will
occur
1/2 clock period
later
(see
Fig_
I ).
Parity
(if
programmed) and stop bit(s) will
be
transmitted following the last data
bit. If the word lengUt selected
is
Jess than 8 bits, the
most
significant
unused bits
in
the
transmitter
shift register
will not
be
transmitted.
One
transmitter
clock
period
after
the Trnnsmitter
Shilt Register
is
loaded
from
the Transmitter
Holding
Register,
the
THRE signal
will
go low and an
interrupt
will
occur (INT goes low). The
next
character
to be transmitted
can t.hen be
loaded into the
Transmilter Hold ing
Register
for
trans-
mission with its
start bi!
immedialely
following the
lasl
stop
bit
of the previous
character.
This cycle
can
be
repea
ted until the
las! character is
transmitted,
at
which
time a
final
THRE
· TSRE
intern1pt
will occur. T11is
interrupt
signals the microprocessor that
TR
can
be turned
off. This
is
done
by
9
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